2mb of conroe cache disabled?

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On the other hand, later in a products lifecycle its common to sell a WORKING core with some cache disabled etc as a lower one to fill volume orders for lower end parts when there are not enough defective ones, hence all the Radeon 9500s that got turned into 9700 Pros.

Also, there are marketing things in other areas hampering the peformance of chips, or all intel CPUs would have been on a 1066 bus for a long time now (given that almost all motherboards support it). The Pentium D 805 for example, had no reason to be on a 533mhz bus other than Intel wanting it to be differentiated from the higher chips.
 
Okay then JKFlipFlop, since you work at Intel, I have a question about the Allendale Core 2 Duos. Of course I know that the Conroes with some bad cache can become Allendales via blowing the Vsupply fuse, but here's what I wonder:

1. I have a suspicion that there are separate Allendale masks that can only make 2MB cache chips as yields on Conroes would be good enough that it would be wasteful to just disable the chip to meet Allendale demand. Is this true?

2. If #1 is true, then give me an estimate (if you can or are allowed to) as to what percentage of Allendales are 2M mask parts and how many are disabled Conroes.

3. If #1 is NOT true, then give me an estimate of how many Conroes that get 2MB of their L2 cache disabled really did have a bad cache and how many were just neutered to meet demand?

Thanks in advance- this is something that I was always curious about ever since there were chips with varying levels of L2 cache starting to be sold.
 
The flip side is the die size is large, so both AMD and Intel will also generate a mask set with smaller die targeted with 2 Meg L2 cache and brand those accordingly as well. In such a case, redundancy is still built in (the cache size is more like 2.5 Meg), but the die size is much smaller and you get higher yields and higher thorougput.

Jack
I have to wonder whether the binned(Conroe) parts with defective cache disabled show any difference in, say overclockability vs a specifically manufactured Allendale, or heat output...required voltage...etc. :?

Good question. I would surmise that since the extra cache is not being used (electrically), it probably would put out the same amount of heat and use the same amount of voltage.

Unless of course the disabled cache is using electricity.

When the extra 2 megs is disabled, one of the fuses that is blown is the Vsupply. No power will be drawn by the disabled memory.

Ohhh yeah I thought they laser cut them but I did hear something about cache using a fuse (of sorts lol) good thinking !!!


They did laser cut them. I remember articles going into nearly microscopic detail on how to reconnect the couple using conductive silver paint to unlock features. I didnt know they were using "fuses" now, but it makes sense . A much better way to prevent a clever kid from buying a E6300 and home brewing his own E6600. It would also save on the equipment as well a remove a physical step from the production line.

Heres an example to unlock the clock mulitplier on an old athlon 2000, but as I recall, they used the same technique on the PII/PIII lines when PIII dies failed QA. They cut em, brand em' as PII and sell em'.

http://www.tomshardware.com/2001/11/12/plastic_surgery/page5.html


Peace
 
Okay then JKFlipFlop, since you work at Intel, I have a question about the Allendale Core 2 Duos. Of course I know that the Conroes with some bad cache can become Allendales via blowing the Vsupply fuse, but here's what I wonder:

1. I have a suspicion that there are separate Allendale masks that can only make 2MB cache chips as yields on Conroes would be good enough that it would be wasteful to just disable the chip to meet Allendale demand. Is this true?

2. If #1 is true, then give me an estimate (if you can or are allowed to) as to what percentage of Allendales are 2M mask parts and how many are disabled Conroes.

3. If #1 is NOT true, then give me an estimate of how many Conroes that get 2MB of their L2 cache disabled really did have a bad cache and how many were just neutered to meet demand?

Thanks in advance- this is something that I was always curious about ever since there were chips with varying levels of L2 cache starting to be sold.

I doubt he could tell u this as this is all yield and binsplit information which is extremely confidential at any manufacturing company. The other issue has to do with customer demand. The binsplit can be completely driver by customer demand and not actual yields. Allendale's are better to make because they have smaller die sizes and therefor you get higher yield and higher volume. But Allendale's can only be sold as 2M. For this reason, they will want to make more Conroe than Allendale, because its always good to have extra 4M versions, b/c they can always be sold as 2M. This allows Intel to have extra 4M versions if all of a sudden demand needs more 4M version that are being sold. If demand needs more 2M versions, they can just be fused as the cheaper 2M slower version. Of course, this is only if binsplit is good enough that they have extra faster parts.
 
Okay then JKFlipFlop, since you work at Intel, I have a question about the Allendale Core 2 Duos. Of course I know that the Conroes with some bad cache can become Allendales via blowing the Vsupply fuse, but here's what I wonder:

1. I have a suspicion that there are separate Allendale masks that can only make 2MB cache chips as yields on Conroes would be good enough that it would be wasteful to just disable the chip to meet Allendale demand. Is this true?

2. If #1 is true, then give me an estimate (if you can or are allowed to) as to what percentage of Allendales are 2M mask parts and how many are disabled Conroes.

3. If #1 is NOT true, then give me an estimate of how many Conroes that get 2MB of their L2 cache disabled really did have a bad cache and how many were just neutered to meet demand?

Thanks in advance- this is something that I was always curious about ever since there were chips with varying levels of L2 cache starting to be sold.

1) You are correct, allendale has it's own mask set.
2) While normally we never discuss such things, I feel that I can boast a little here and tell you that less than 5% of conroe ends up in the bargain bin. the rest are allendales.
 
Yup, that's all I wanted to know! 😀 Not trying to undertake corporate sabotage or data mining- just curious. I have read that modern CPU production results in very few defect chips- apparently this is very true and that the price considerations drive a separate mask set.

Thanks for the info, and kudos to a job well done!
 
Yup, that's all I wanted to know! 😀 Not trying to undertake corporate sabotage or data mining- just curious. I have read that modern CPU production results in very few defect chips- apparently this is very true and that the price considerations drive a separate mask set.

Thanks for the info, and kudos to a job well done!

While a lot of this has to do with CPU production, a lot of this is also due to redundancy. It would take a MAJOR cache failure in order for it to not be recovered using cache recovery. Almost all cache failures can be fixed by using the extra cache banks that are included on the CPU.
 
imagine poor kids in africa with crankable Prescotts. LOLLLOLS that's a lotttt of cranking kids!!

Pitch that idea to school boards all across the U.S. Having kids in classes cranking while the others are using. It could take the place of gym class! And maybe slim down some o the fat ones.
 
imagine poor kids in africa with crankable Prescotts. LOLLLOLS that's a lotttt of cranking kids!!

Pitch that idea to school boards all across the U.S. Having kids in classes cranking while the others are using. It could take the place of gym class! And maybe slim down some o the fat ones.

You meant North America or Canada. because I'm in Canada.

Ofcourse it'll be a new way to work out It'll sure make them slim if not Armstrong. Maybe America will have lost enough wait to compete with Poor African kids in a weight off (World's skinniest Country) USA vs Sudan :twisted: