News AMD Comes Roaring Back: Analyzing CPU Sales at Mindfactory Over the Last Five Years

[kinggremlin]

Yes it is a fixed number.

Intel disagrees with you.

The thing that depends on a variety of factors, e.g. what type of instruction being executed is the performance(per core) .
It's like saying horsepower is the same as mph but ipc/horsepower always stays the same while performance/mph depends on what you do.

Biggest issue for ryzen is that the 9900k has another 25% in clock overhead while the ryzen maybe has 10% at best.
*all core

Your HP analogy makes no sense. Regardless of the actual definition of IPC, the way it is used in the industry is the performance of a CPU at a given clock rate compared to another CPU at that same clock rate. You will never see a CPU manufacturer state IPC as a whole number as it varies greatly depending on the code that is run, so I don't know where you got an increase from 4 to 5 for Sunny Cove. TJ Hooker asked you where you got that from, and you oddly ignored his question. So again, where did you get those numbers from? IPC is always given as a relative comparison to something else. If CPU X benchmarks 10% better on average than CPU Y at the same clock rate, then by definition it has 10% higher IPC.

Here is what Intel is actually claiming about Sunny Cove's IPC:

It's not a fixed number. Depending on the test run, Sunny Cove has an IPC vs Sky Lake of anything between slightly slower all the way up to 40% faster, with the average coming in at 18%.

 

[TerryLaze]

No, it's not. Performance (instructions/operations per second) = IPC x clock speed. Given that performance obviously varies from one load to the next, even with constant frequency, it's obvious that effective IPC must vary as well.

Why are you starting with no it's not if everything you say agrees with me?
"The thing that depends on a variety of factors, e.g. what type of instruction being executed is the performance"
"performance obviously varies from one load to the next, even with constant frequency, it's obvious that effective IPC must vary as well"

Performance (instructions/operations per second) = IPC x clock speed.

You can only do IPC x clock speed if it constantly uses the same amount of instructions,if the amount varies during the run it will start getting very messy.
What intel uses is instructions retired divided by number of active cycles, PCM is an intel tool

And even if it was a fixed number (it's not), I'll again ask for a source for your claim that Intel's IPC went from 4 to 5.

Both companies always make this public, you can look up how many instructions each arch has in parallel.
If you make a perfect piece of software,then the effective IPC as you call it would be equal to the maximum IPC the CPU can provide.
Skylake would top out at allocating/fetching 4 instructions out of a pool of 8 instructions while sunny top out at 5 out of 10.

And yes of course I am aware that it is a lot more complicated than just the amount of instructions you have available,that's why the maximum IPC a core can provide can never be tapped by normal software(no software ever improves it's effective IPC as much as the actual IPC improves) ,but that does not change the fact that companies add actual instructions to their cores in parallel.

https://www.tomshardware.com/reviews/intel-sunny-cove-gen11-xe-gpu-foveros,5932-4.html

Also, your analogy is a poor one, as the power output (hp) of a motor is not constant (varies with RPM, air-fuel ratio, etc).

The amount you can get out of it is not the maximum,yes welcome to reality, nobody has yet to invent anything with 0% loss in energy,when you buy a car it will still state a fixed hp number and not a range.
Look at PCM that's why they look at the actual amount of cycles that are active(any usage from any piece of software) and not at the clock speed,because looking at the clock speed would mix in inactive cycles,cycles that none of the software that is currently running is using.
Yup take a guess, that's something all these "locked at X Ghz" benchmarks just brush under the table.

 

[TJ Hooker]

Well, first off, the 4 or 5 wide allocation is micro-ops. So even if you assume that you have magical code that can be perfectly parallelized, all data required is already in cached, etc., that's not the same executing 4/5 instructions per cycle. And different instructions will entail different numbers of micro-ops.

Regardless, you repeatedly stated that Intel's IPC is a fixed number and yet we have Intel's own slides explicitly showing otherwise. But in response you simply move your goalposts. Either you're a troll or you're incapable of admitting you were mistaken, either way I'm done arguing.