AMD CPU speculation... and expert conjecture

[sarinaide]

So far AMD have shown what can be achieved on an APU, despite its limitations. If AMD is to find a way to unlock its performance which is largely hindered by the antiquated Bus and Memory controller and if say was able to double and possibly go beyond that then the APU's will be light years ahead of what anyone else can produce to do something of similar calibre. Steamroller FX as eluded to doesn't exist because AMD are playing to their strength, the APU represents something feasible to persue because the potential is there and waiting to be unlocked.

 

[gamerk316]

APU might be much faster because it doesn't have to go over horrendously slow PCIe 3.0 bus. But the point I'm making is that if PCIe is replaced with something that would alleviate that bottleneck and transfer it back to something like system memory, the dGPU and dCPU would be a vastly superior option.

The PCIe 2.0 bus isn't even being saturated much less the PCIe 3.0 bus. Bandwidth isn't an issue at all right now, at least for consumer computing. The real issue is latency when your trying to use HSA style computing on dGPU's because you can stall your code stream out. A dGPU is an offboard high powered processor, lots of bandwidth and capability but the turn around time is much larger then if the processor was on the same die. On the flip side, it's physically impossible to get the dGPU's level of power on the same die as the CPU. So the dGPU will never become obsolete, it may become less common or a specialized solution, but it will never die off.

PCI-E 2.0? Heck, PCI-E 1.1 hasn't even been saturated for non-Titan cards yet. Bandwidth of the bus isn't a huge problem at this point.

 

[logainofhades]

An HD 7970 and GTX 680 push the limits of 1.1, but the performance difference still isn't huge vs 2.0 or 3.0. I would want 3.0 for Crossfired 290 or 290x since the CF bridge is gone from those and the data passes across the PCI-E lanes instead.

 

[juanrga]

Thus Nvidia is migrating from traditional, slow and power-hungry, CPU plus GPUs card architecture to a network made of CPUs and GPUs and finally will migrate to a network of APUs.

Everything is going just as planned...

Considering NVidias GPU and Mobile roadmaps just completely changed overnight I wouldn't call that "just as planned".

I am referring to the big plan of migrating away from the current discrete cards to the ultra-high-performance APU that Daily and his team are designing. Irrelevant details such as if X is released at concrete year or if it is delayed one or two years don't change the overall long-term plan.

This is the same than with AMD and their plan to go from CPU+GPU to "Step 3" APU (check the former AMD slide). The big plan has not changed, only details such as that Kaveri was not the successor of Trinity as initially planned by AMD, but Richland was introduced in the middle due to Kaveri delays. Nvidia is introducing Pascal and Erista by similar reasons.

And that special high speed link isn't that different than PCIe 4.0. It's 20GT/s instead of 16GT/s.

That is per lane. PCIe 4.0 will max at 256 GT/s = 31.51 GB/s, whereas NVLINK will max at 200GB/s. This is up to 6x more than PCIe 4.0 and up to 12x more than current PCie 3.0.

The difference is larger for multi-GPU configurations where NVLINK will max at 800GB/s (for four GPUs), whereas a PCIe switch divides the total bandwidth between the GPUs:

In a multi-GPU system, the problem is compounded if a PCIe switch is used. With a switch, the limited PCIe bandwidth to the CPU memory is shared between the GPUs.

Moreover, it provides other advantages such as improved efficiency: 2x.

"The end result is a bus that looks a whole heck of a lot like PCIe, and is even programmed like PCIe, but operates with tighter requirements and a true point-to-point design. NVLink uses differential signaling (like PCIe), with the smallest unit of connectivity being a block. A block contains 8 lanes, each rated for 20Gbps, for a combined bandwidth of 20GB/sec. In terms of transfers per second this puts NVLink at roughly 20 gigatransfers/second, as compared to an already staggering 8GT/sec for PCIe 3.0, indicating at just how high a frequency this bus is planned to run at."


You're looking at a fairly high density mezzanine connector to hook these things together with 32 differential channels and all the extra grounds for signal integrity. You're looking at roughly double the connections for a PCIe x16 slot or ~160 pins. Probably even more pins because they'll need more power. PCIe can do this with fewer pins because they have auxilliary giant molex power connectors. Those fat 6 and 8 pin connectors can carry more juice.

You say it's getting away from discrete GPUs cards plugged in PCIe slots when it's more like GPU modules plugged on even wider/fatter mezzanines.

The same source that you quote and link to image agrees with me:

To pull off the kind of transfer rates NVIDIA wants to accomplish, the traditional PCI/PCIe style edge connector is no good; if nothing else the lengths that can be supported by such a fast bus are too short. So NVLink will be ditching the slot in favor of what NVIDIA is labeling a mezzanine connector, the type of connector typically used to sandwich multiple PCBs together (think GTX 295). We haven’t seen the connector yet, but it goes without saying that this requires a major change in motherboard designs for the boards that will support NVLink. The upside of this however is that with this change and the use of a true point-to-point bus, what NVIDIA is proposing is for all practical purposes a socketed GPU, just with the memory and power delivery circuitry on the GPU instead of on the motherboard.

I already explained before why both Intel and AMD are migrating to APU directly, whereas Nvidia needs the intermediate step of a socketed GPU:

Discrete GPU Card --> socketed GPU --> ultra-high-performance APU

The funny part is not on that AMD head did the correct thing and that AMD is now live, away from red, and with good financial credibility, but that it is Intel which is having serious problems with their foundry business and are anxiously looking for new markets to minimize the huge loses per month. Their need of money is so big than are opening foundries to competitors such as ARM.

April fools isn't for 5 more days. Surely you can't be serious. Intel is not losing money. They are still making money hand over fist and paying record dividends (4.5B in 2013). Their margins went down like 2.3%.

I am not referring to overall balance, which is still positive, but to the huge loses that Intel has per month due to their empty fabs and which forced they to open their fabs

http://www.brightsideofnews.com/news/2013/11/21/intel-finally-opens-up-fabs2c-details-mobile-push.aspx

 

[gamerk316]

Since the issue of yields has come up:

http://www.extremetech.com/computing/171477-intels-14nm-milkshake-its-better-than-yours

 

[juanrga]

Since the issue of yields has come up:

http://www.extremetech.com/computing/171477-intels-14nm-milkshake-its-better-than-yours

Here relevant correction to Intel slide

https://www.semiwiki.com/forum/content/3099-tsmc-responds-intel-s-14nm-density-claim.html

 

[Cazalan]

I am referring to the big plan of migrating away from the current discrete cards to the ultra-high-performance APU that Daily and his team are designing. Irrelevant details such as if X is released at concrete year or if it is delayed one or two years don't change the overall long-term plan.

This is the same than with AMD and their plan to go from CPU+GPU to "Step 3" APU (check the former AMD slide). The big plan has not changed, only details such as that Kaveri was not the successor of Trinity as initially planned by AMD, but Richland was introduced in the middle due to Kaveri delays. Nvidia is introducing Pascal and Erista by similar reasons.

Yes we get that circuits will become more integrated over time. That's just how computing has evolved since day one. It is not some big special plan devised. That's just how electronics is.

That is per lane. PCIe 4.0 will max at 256 GT/s = 31.51 GB/s, whereas NVLINK will max at 200GB/s. This is up to 6x more than PCIe 4.0 and up to 12x more than current PCie 3.0.

The difference is larger for multi-GPU configurations where NVLINK will max at 800GB/s (for four GPUs), whereas a PCIe switch divides the total bandwidth between the GPUs:

In a multi-GPU system, the problem is compounded if a PCIe switch is used. With a switch, the limited PCIe bandwidth to the CPU memory is shared between the GPUs.

Moreover, it provides other advantages such as improved efficiency: 2x.

Yes I specifically called out per lane speeds. You are aware that you can make a 32 lane PCIe slot right? It's supported by the standard. You are feeding into the marketing claims hook line and sinker. Nvidia is touting a late 2016 link that is slighty faster than PCIe 4.0. The higher speed NVLink you're referring to is a 2.0 which will be even later, maybe late 2018.

The same source that you quote and link to image agrees with me:

To pull off the kind of transfer rates NVIDIA wants to accomplish, the traditional PCI/PCIe style edge connector is no good; if nothing else the lengths that can be supported by such a fast bus are too short. So NVLink will be ditching the slot in favor of what NVIDIA is labeling a mezzanine connector, the type of connector typically used to sandwich multiple PCBs together (think GTX 295). We havent seen the connector yet, but it goes without saying that this requires a major change in motherboard designs for the boards that will support NVLink. The upside of this however is that with this change and the use of a true point-to-point bus, what NVIDIA is proposing is for all practical purposes a socketed GPU, just with the memory and power delivery circuitry on the GPU instead of on the motherboard.

Without a ZIF (zero insertion force) socket and latchiing arm it's not a socket to me. That's a board to board connector very much like 2xPCIe.

I am not referring to overall balance, which is still positive, but to the huge loses that Intel has per month due to their empty fabs and which forced they to open their fabs

http://www.brightsideofnews.com/news/2013/11/21/intel-finally-opens-up-fabs2c-details-mobile-push.aspx

[/quotemsg]

9B pocketed after all expenses paid is more than just positive. That's incredible.

How is an empty fab a huge loss? There are no employees in it. They have no expenses besides land taxes. The property still has value that will continue to grow as the USA becomes more populated.

The world doesn't stand still. Every business model changes over time. When every silicon vendor had their own fabs there was no need to offer services to other companies. Now that they've all gone fabless the opportunity presents itself. Why would Intel just give all that business away to TSMC/GF?

 

[juanrga]

Spoiler

The next big thing, as I have been saying in this thread forever, is a fabric that can get dGPUs and dCPUs working together heterogeneously.

No one has really believed me at all, but guess what? Nvidia has already done it with Nvidia NvidiaLink! They're doing the same exact thing I predicted would happen.

Yet some of you insisted that APUs were the only solution forever, while I claimed that APU was a stopgap for something bigger because there currently isn't a good interconnect for dGPU and dCPU.

They are going to come. AMD is going to come up with a really good workstation/professional and HPC solution and it's going to get retrofitted into HEDT.

AMD is far from done. L3 cache takes up around half of Vishera die, and it serves very little purpose since it's barely faster than system memory (although the latency is better). L3$ could easily be replaced with modules on excavator or something while still using 32nm and AMD would have a roughly 300mm^2 die with 8m/16c.

And if AMD threw HDL into the mix it might actually end up smaller.

As it was showed in this thread, AMD, Intel, and Nvidia are migrating away from dCPUs + dGPUs to ultra-high-performance APUs. Let me recall that the ultra-high-performance APU that Nvidia is designing has ~40 TFLOPS of performance. The new Titan Black GPU only has ~5 TFLOPS ;-)

Each company (intel, Nvidia, and AMD) is designing an ultra-high-performance APU that will replace their corresponding dGPU (or Phi for Intel). The reason for the abandon of discrete cards was mentioned as well: the ultra-high-performance APU will provide about 10x more performance than fastest dCPU+dGPU design possible.

Intel is migrating directly from discrete card to APU

AMD has been planning the same for years

Nvidia cannot do it, because their own high-performance CPU (Boulder cores?) is not ready at this time. They only have ready the Denver cores for Tegra APUs. But those are mobile/tablet APUs.

Nvidia has to rely on another CPU maker at this time. Evidently neither Intel nor AMD will do collaborate with Nvidia. However IBM will do, because IBM joined Nvidia to compete against Intel on HPC market. Integrating CPU and GPU on die is very difficult, just look how many years it took to AMD to integrate graphics with CPUs (check above image) and still integration is not complete (luckily Carrizo APU will do finally); moreover integration of CPU and GPU on same die would limit flexibility of partnership of IBM or Nvidia each with other people.

The solution? An intermediate step between the traditional dCPU+dGPU design and the future ultra-high-performance APU that Nvidia is designing. This is what Nvidia presents today. An interconnect that basically means that they are moving to socketed GPU:

GPU on PCIe card (traditional) --> GPU on socket --> GPU on die (ultra-high-performance APU).

In fact, the NVLINK has been designed by Nvidia's Daily, the same scientist who is leading the Nvidia team designing their ultra-high-performance APU. Their ultra-high-performance APU is so fast that doesn't use a traditional bus system to connect CPU and GPU cores, but use a special network on chip to build a heterogeneous fabric.

The new NVLINK share parts of that ultra-high-performance APU design and unsurprisingly allows for developing CPU-CPU and CPU-GPU networks

The links can be ganged together to form a single GPU↔CPU connection or used individually to create a network of GPU↔CPU and GPU↔GPU connections allowing for fast, efficient data sharing between the compute elements.

http://devblogs.nvidia.com/parallelforall/nvlink-pascal-stacked-memory-feeding-appetite-big-data/

Thus Nvidia is migrating from traditional, slow and power-hungry, CPU plus GPUs card architecture to a network made of CPUs and GPUs and finally will migrate to a network of APUs.

Everything is going just as planned...

Yeah, the thing is, I'm making the claim that APU is significantly faster because it doesn't share the significant bottleneck that dCPU and dGPU have of having to go over a very slow bus.

APU might be much faster because it doesn't have to go over horrendously slow PCIe 3.0 bus. But the point I'm making is that if PCIe is replaced with something that would alleviate that bottleneck and transfer it back to something like system memory, the dGPU and dCPU would be a vastly superior option.

But we need a fabric like that regardless. A single APU might beat dGPU and dCPU over PCIe, but if you want to use one APU, you are still screwed and need that faster link.

I have heard from a random IBM employee that AMD is also working with IBM to make some sort of really fast bus to solve this problem.

But just leaving things at one APU to transfer over ancient HT 3.0 or PCIe is not going to work.

Even if AMD ends up going multiple APUs, they will want to make sure that all the APUs can speak to each other with as little bottleneck as possible.

Unless you think we're going to see HPC evolve into one giant APU, AMD and Intel are going to have to come up with something like Nvidia NvidiaLink.

It might not end up dGPU working with dCPU, but at the very least we will get APU working with APU along the lines of "I have a system with 4 4m/8c Excavator cores and 1024 GCN cores, giving me 16m/32c and 4096 GCN core system" and they all work together as one heterogeneous system.

But my point is that if you can get rid of the bottleneck between chips, there's no reason why you can't have a big dCPU with a big dGPU, or any combination of them. In fact we're sort of seeing it with what Intel is doing as well.

But I think you are misunderstanding me a little Juan, I don't think this is going to happen right away. I think we will get a generation or two of APU only set ups and then we will migrate to what I am talking about. Which is why we have no new HEDT platform from AMD right now. They don't have anything special they can do other than MOAR COARS and MOAR JIGGAHURTZ so there's no point in doing anything other than waiting until they get infiniband over hypertransport up and running or something.

The PCIe bottleneck is only one of the problems, and the minor of them. Upgrading to a new PCIe or to a new interconnect as NVLINK doesn't solve the power wall problem for exascale. I already mentioned plenty of times which is the solution.

The same Nvidia guy who has designed NVLINK is the same guy who is not using any dGPU for Nvidia exascale supercomputer project. AMD chief engineer has also selected an APU and rejected any dGPU for AMD supercomputer. Thus either you think you know more than both of them or, alternatively, you could read my dozen of posts about the topic that explain why a dGPU doesn't work for exascale compute.

Their APUs are not connecting each other "over ancient HT 3.0 or PCIe". The Nvidia APU docs mention an interconnect of 150GB/s. The AMD docs mention one of 40--100GB/s. This is bandwith available for each APU, not shared among all of them.

The NVLINK presented now seems to be derived from their future APU-APU interconnect.

 

[juanrga]

I am referring to the big plan of migrating away from the current discrete cards to the ultra-high-performance APU that Daily and his team are designing. Irrelevant details such as if X is released at concrete year or if it is delayed one or two years don't change the overall long-term plan.

This is the same than with AMD and their plan to go from CPU+GPU to "Step 3" APU (check the former AMD slide). The big plan has not changed, only details such as that Kaveri was not the successor of Trinity as initially planned by AMD, but Richland was introduced in the middle due to Kaveri delays. Nvidia is introducing Pascal and Erista by similar reasons.

Yes we get that circuits will become more integrated over time. That's just how computing has evolved since day one. It is not some big special plan devised. That's just how electronics is.

Except that it is about how exascale is substantially different instead a mere extrapolation (integration) of current tech.

That is per lane. PCIe 4.0 will max at 256 GT/s = 31.51 GB/s, whereas NVLINK will max at 200GB/s. This is up to 6x more than PCIe 4.0 and up to 12x more than current PCie 3.0.

The difference is larger for multi-GPU configurations where NVLINK will max at 800GB/s (for four GPUs), whereas a PCIe switch divides the total bandwidth between the GPUs:

In a multi-GPU system, the problem is compounded if a PCIe switch is used. With a switch, the limited PCIe bandwidth to the CPU memory is shared between the GPUs.

Moreover, it provides other advantages such as improved efficiency: 2x.

Yes I specifically called out per lane speeds. You are aware that you can make a 32 lane PCIe slot right? It's supported by the standard. You are feeding into the marketing claims hook line and sinker. Nvidia is touting a late 2016 link that is slighty faster than PCIe 4.0. The higher speed NVLink you're referring to is a 2.0 which will be even later, maybe late 2018.

Even comparing NVLINK to a 32 lane PCIe slot, PCIe continue being much more slower. If you believe that IBM has purchased NVLINK because Nvidia marketing team fooled them, instead because it is better than PCIe, then that is funny.

The same source that you quote and link to image agrees with me:

To pull off the kind of transfer rates NVIDIA wants to accomplish, the traditional PCI/PCIe style edge connector is no good; if nothing else the lengths that can be supported by such a fast bus are too short. So NVLink will be ditching the slot in favor of what NVIDIA is labeling a mezzanine connector, the type of connector typically used to sandwich multiple PCBs together (think GTX 295). We havent seen the connector yet, but it goes without saying that this requires a major change in motherboard designs for the boards that will support NVLink. The upside of this however is that with this change and the use of a true point-to-point bus, what NVIDIA is proposing is for all practical purposes a socketed GPU, just with the memory and power delivery circuitry on the GPU instead of on the motherboard.

Without a ZIF (zero insertion force) socket and latchiing arm it's not a socket to me. That's a board to board connector very much like 2xPCIe.

Both Anand and myself know what is a socket. Wasn't evident?

I am not referring to overall balance, which is still positive, but to the huge loses that Intel has per month due to their empty fabs and which forced they to open their fabs

http://www.brightsideofnews.com/news/2013/11/21/intel-finally-opens-up-fabs2c-details-mobile-push.aspx

9B pocketed after all expenses paid is more than just positive. That's incredible.

How is an empty fab a huge loss? There are no employees in it. They have no expenses besides land taxes. The property still has value that will continue to grow as the USA becomes more populated.

The world doesn't stand still. Every business model changes over time. When every silicon vendor had their own fabs there was no need to offer services to other companies. Now that they've all gone fabless the opportunity presents itself. Why would Intel just give all that business away to TSMC/GF?

The link given above already explain why Intel is opening its empty fabs to competitors.

 

[jdwii]

I like the 250X i can now build a machine for 400$(402$) with all new parts that includes a Pentium dual core haswell and a 250x and it can play all games at 1080P medium with really good performance. Plus Intel's cheap boards are now worth getting i like the 50$ asus board(ASUS H81M-K) i got. This will make one heck of an PC for my brother and it has an amazing upgrade path so if he wants to get one of the fastest processors in the world he can.
I might run some gaming benchmarks later but i can tell its definitely a Superior machine compared to the APU A10 7850K in gaming while feeling a little slower in general multitasking and applications.

 

[Cazalan]

Spoiler

Even comparing NVLINK to a 32 lane PCIe slot, PCIe continue being much more slower. If you believe that IBM has purchased NVLINK because Nvidia marketing team fooled them, instead because it is better than PCIe, then that is funny.

It's only 25% faster than PCIe 4.0. That's hardly anything.

An Infiniband link is 25GT/s, so NVlink (20GT/s) is actually slower than Infiniband which has been around for several years now. So sure NVidia didn't want to pay Intel for that or they couldn't and were forced to reinvent the wheel.

Spoiler

Both Anand and myself know what is a socket. Wasn't evident?

Anything containing a cavity which an inserted part can fit, is a socket. So yes a mezzanine card (Pascal) can be called socketed, and a CPU is socketed, and even a PCI card is socketed.

In computing we tend to be a little more specific in terminology, but whatever floats your boat. Either way it's an entire PCB plugging into another PCB, just like a dGPU card.

Spoiler

The link given above already explain why Intel is opening its empty fabs to competitors.

Yeah I read the article when it came out. No where did it mention huge losses. They're capitalizing on new opportunities.

 

[de5_Roy]

I like the 250X i can now build a machine for 400$(402$) with all new parts that includes a Pentium dual core haswell and a 250x and it can play all games at 1080P medium with really good performance. Plus Intel's cheap boards are now worth getting i like the 50$ asus board(ASUS H81M-K) i got. This will make one heck of an PC for my brother and it has an amazing upgrade path so if he wants to get one of the fastest processors in the world he can.
I might run some gaming benchmarks later but i can tell its definitely a Superior machine compared to the APU A10 7850K in gaming while feeling a little slower in general multitasking and applications.

has amd enabled mantle support for r7 250x? it could be a good test to see how much the pentium bottlenecks the 250x with dx11. right now, only bf4 and thief are mantle-enabled. according to a recent xbitlabs testing, thief may be system memory bound (in dx11, dunno about mantle).

ofc it'll be better than 7850k... in gpu performance, due to current prices. but if you could get a 7850k from microcenter (only applies to people near mc), the favor tips towards the kaveri.

 

[truegenius]

I like the 250X i can now build a machine for 400$(402$) with all new parts that includes a Pentium dual core haswell and a 250x and it can play all games at 1080P medium with really good performance. Plus Intel's cheap boards are now worth getting i like the 50$ asus board(ASUS H81M-K) i got. This will make one heck of an PC for my brother and it has an amazing upgrade path so if he wants to get one of the fastest processors in the world he can.
I might run some gaming benchmarks later but i can tell its definitely a Superior machine compared to the APU A10 7850K in gaming while feeling a little slower in general multitasking and applications.

i7-4960X ?

 

[juanrga]

Spoiler

Even comparing NVLINK to a 32 lane PCIe slot, PCIe continue being much more slower. If you believe that IBM has purchased NVLINK because Nvidia marketing team fooled them, instead because it is better than PCIe, then that is funny.

It's only 25% faster than PCIe 4.0. That's hardly anything.

An Infiniband link is 25GT/s, so NVlink (20GT/s) is actually slower than Infiniband which has been around for several years now. So sure NVidia didn't want to pay Intel for that or they couldn't and were forced to reinvent the wheel.

It is more like 200% faster than single 32 lane PCIe 4.0. And much more in multi-GPU conf.

Years ago, Nvidia collaborated with Mellanox to reduce Infiniband bottlenecks.

Latter, Nvidia rejected the usual infiniband interconnect for a newest Dragonfly interconnect for the modules in their exascale supercomputer. Of course, both infiniband and Dragonfly are too slow for APU-APU interconnects and Nvidia developed NVLINK for that and presented it now for CPU--GPU and GPU--GPU interconnect.

Before you pretended that IBM is full of idiots who purchased NVLINK when PCie is about the same. Now you pretend that IBM people is full of idiots who purchased NVLINK when infiniband is much better. Funny, because IBM has been using infiniband for years, including in the lastest Power7 HPC clusters...

Spoiler

Both Anand and myself know what is a socket. Wasn't evident?

Anything containing a cavity which an inserted part can fit, is a socket. So yes a mezzanine card (Pascal) can be called socketed, and a CPU is socketed, and even a PCI card is socketed.

In computing we tend to be a little more specific in terminology, but whatever floats your boat. Either way it's an entire PCB plugging into another PCB, just like a dGPU card.

Spoiler

The link given above already explain why Intel is opening its empty fabs to competitors.

Yeah I read the article when it came out. No where did it mention huge losses. They're capitalizing on new opportunities.

Right, "huge losses" were mentioned by me. They use terms such as "doom and gloom" and "dismaying investors" that "have to worry less about Intel having empty fabs". The article summarize the problem already in the first paragraph. Thus I doubt that you did read the article.

 

[8350rocks]

@juanrga:

Ironically, you are telling me EXACTLY the opposite of what AMD is telling me, HEDT is NOT dead...they are just waiting until a better time to get things going presents itself.

I would trust word from AMD over your speculations any day of the week and twice on Sunday. They may not launch a new HEDT product this year...but it IS coming.

 

[truegenius]

@juanrga:

Ironically, you are telling me EXACTLY the opposite of what AMD is telling me, HEDT is NOT dead...they are just waiting until a better time to get things going presents itself.

I would trust word from AMD over your speculations any day of the week and twice on Sunday. They may not launch a new HEDT product this year...but it IS coming.

how you see it

how I see it

it IS coming.

it IS coming.

 

[Cpus]

Is AMD going to release a desktop processor with Steamroller?

 

[de5_Roy]

Is AMD going to release a desktop processor with Steamroller?

amd did. amd a10 7850k and 7700k have steamroller cpu cores inside the apus.

 

[sarinaide]

Now we are up to excavator speculation, would it be the same 28nm or possibly a jump to 22/20nm?

 

[vmN]

Now we are up to excavator speculation, would it be the same 28nm or possibly a jump to 22/20nm?

I'm pretty sure it is still gonna be 28nm. That all GloFo can offer currently.

 

[jdwii]

Now we are up to excavator speculation, would it be the same 28nm or possibly a jump to 22/20nm?

I'm pretty sure its going to be on 28nm this time around. I can't wait to see what's coming out after excavator. I'm actually guessing Amd won't be releasing any high end processors until this module design is over with. I'm not to sure whats happening at Amd i know some engineers did want a high end processor out but things did not work out right. I see the business guys still overrun the engineering department at Amd, i guess its better then the marketing guys doing it.

 

[Cazalan]

Spoiler

It is more like 200% faster than single 32 lane PCIe 4.0. And much more in multi-GPU conf.

Years ago, Nvidia collaborated with Mellanox to reduce Infiniband bottlenecks.

Latter, Nvidia rejected the usual infiniband interconnect for a newest Dragonfly interconnect for the modules in their exascale supercomputer. Of course, both infiniband and Dragonfly are too slow for APU-APU interconnects and Nvidia developed NVLINK for that and presented it now for CPU--GPU and GPU--GPU interconnect.

Before you pretended that IBM is full of idiots who purchased NVLINK when PCie is about the same. Now you pretend that IBM people is full of idiots who purchased NVLINK when infiniband is much better. Funny, because IBM has been using infiniband for years, including in the lastest Power7 HPC clusters...

You're failing at simple math here. NVlink 1.0 is 20GT/s. PCIe 4.0 is 16GT/s. That makes it 25% faster.

Infiniband is 25GT/s. What's worse is you're comparing tech 2+ years into the future with what has already been in shipping product for a while now.

The even farther future NVlink 2.0 where the 50GT/s speed comes (the 200% you're talking about) is like 2019 tech. Infiniband already has 50GT/s slated for 2017. BTW this is just one competing solution.

You're the only one talking about idiots here. Those are your words not mine. NVidia wants to brand their own version of a high speed serial interconnect that's fine. It makes it easier to market. It's a solid tie in with IBMs powerful sales channels.

Just don't misrepresent the facts and make it sound like something completely new and unique to NVidia. There are down sides as well to NVLink. I'll just mention one minor one to start. 99.9999% of PC's in 2016 will not have a NVLink port for this thing to plug into, so they will have to make a PCIe version. Conveniently NVLink ports can talk PCIe, so you see how similar they really are.

Spoiler

Right, "huge losses" were mentioned by me. They use terms such as "doom and gloom" and "dismaying investors" that "have to worry less about Intel having empty fabs". The article summarize the problem already in the first paragraph. Thus I doubt that you did read the article.

"While many have claimed doom and gloom on the PC market, Intel has proven that they haven't seen nearly as much volatility in the market as some of their competitors have."

Are you even reading the same article? That's saying despite all the fear mongering, they haven't really been that affected. Their revenue actually went up last year.

The phrasing "while many have claimed" means they are taking a neutral stance. People love doom and gloom articles. They get lots of hits, and apparently you feed right into them as well.

 

[8350rocks]

Supposedly...(BIG word here)...GF will have 20/22nm online for proofing by Q3/Q4 this year...we shall see what happens...I will not hold my breath for anything relating to GF these days though...

 

[jimmysmitty]

How are they copying AMD? Devils Canyon only pushes the speed up 100MHz, much like with the i7 2600K to i7 2700K.

If they were to copy AMD they would just release a 4GHz stock overclocked part which I don't see listed in the parts at all.

Where did you see numbers for Devil's Canyon? The 100MHz clock bump is for Haswell refresh parts, not Devil's Canyon.

"re-engineering refers to improved thermal interface and CPU packaging materials that are expected to enable significant enhancements to performance and overclocking capabities"

I don't think anyone would consider 100Mhz "significant" but we'll see.

http://www.tomshardware.com/news/intel-haswell-e-devils-canyon-pentium-anniversary-edition-broadwell,26326.html

Can't find where I saw the frequency changes to the Haswell refresh but Devils Canyon is just part of that refresh. I doubt it is some insane OC CPU but they might be improving the thermal transfer of it.

An HD 7970 and GTX 680 push the limits of 1.1, but the performance difference still isn't huge vs 2.0 or 3.0. I would want 3.0 for Crossfired 290 or 290x since the CF bridge is gone from those and the data passes across the PCI-E lanes instead.

I think AMD made a smart move in removing the need for a bridge and finally using the PCIe interface only. NVidia should honestly do the same.

 

[anxiousinfusion]

Now we are up to excavator speculation, would it be the same 28nm or possibly a jump to 22/20nm?

Not my speculation but BSN's:

Given we know that Carrizo will be manufactured at the 28nm node, albeit a different process than Kaveri, it is unlikely AMD adds more compute units to the GPU.

Apparently Global Foundries as well as TSMC are having difficulty producing 20nm/16nm that suit the needs of high performance parts.