blackkstar :
The next big thing, as I have been saying in this thread forever, is a fabric that can get dGPUs and dCPUs working together heterogeneously.
No one has really believed me at all, but guess what? Nvidia has already done it with Nvidia NvidiaLink! They're doing the same exact thing I predicted would happen.
Yet some of you insisted that APUs were the only solution forever, while I claimed that APU was a stopgap for something bigger because there currently isn't a good interconnect for dGPU and dCPU.
They are going to come. AMD is going to come up with a really good workstation/professional and HPC solution and it's going to get retrofitted into HEDT.
AMD is far from done. L3 cache takes up around half of Vishera die, and it serves very little purpose since it's barely faster than system memory (although the latency is better). L3$ could easily be replaced with modules on excavator or something while still using 32nm and AMD would have a roughly 300mm^2 die with 8m/16c.
And if AMD threw HDL into the mix it might actually end up smaller.
As it was showed in this thread, AMD, Intel, and Nvidia are migrating away from dCPUs + dGPUs to ultra-high-performance APUs. Let me recall that the ultra-high-performance APU that Nvidia is designing has ~40 TFLOPS of performance. The new Titan Black GPU only has ~5 TFLOPS ;-)
Each company (intel, Nvidia, and AMD) is designing an ultra-high-performance APU that will replace their corresponding dGPU (or Phi for Intel). The reason for the abandon of discrete cards was mentioned as well: the ultra-high-performance APU will provide about
10x more performance than fastest dCPU+dGPU design possible.
Intel is migrating directly from discrete card to APU
AMD has been planning the same for years
Nvidia cannot do it, because their own high-performance CPU (Boulder cores?) is not ready at this time. They only have ready the Denver cores for Tegra APUs. But those are mobile/tablet APUs.
Nvidia has to rely on another CPU maker at this time. Evidently neither Intel nor AMD will do collaborate with Nvidia. However IBM will do, because IBM joined Nvidia to compete against Intel on HPC market. Integrating CPU and GPU on die is very difficult, just look how many years it took to AMD to integrate graphics with CPUs (check above image) and still integration is not complete (luckily Carrizo APU will do finally); moreover integration of CPU and GPU on same die would limit flexibility of partnership of IBM or Nvidia each with other people.
The solution? An intermediate step between the
traditional dCPU+dGPU design and the future ultra-high-performance APU that Nvidia is designing. This is what Nvidia presents today. An interconnect that basically means that they are moving to
socketed GPU:
GPU on PCIe card (traditional) --> GPU on socket --> GPU on die (ultra-high-performance APU).
In fact, the NVLINK has been designed by Nvidia's Daily,
the same scientist who is leading the Nvidia team designing their ultra-high-performance APU. Their ultra-high-performance APU is so fast that doesn't use a traditional bus system to connect CPU and GPU cores, but use a special network on chip to build a heterogeneous fabric.
The new NVLINK share parts of that ultra-high-performance APU design and unsurprisingly allows for developing CPU-CPU and CPU-GPU networks
The links can be ganged together to form a single GPU↔CPU connection or used individually to create a network of GPU↔CPU and GPU↔GPU connections allowing for fast, efficient data sharing between the compute elements.
http://devblogs.nvidia.com/parallelforall/nvlink-pascal-stacked-memory-feeding-appetite-big-data/
Thus Nvidia is migrating from traditional, slow and power-hungry, CPU plus GPUs card architecture to a network made of CPUs and GPUs and finally will migrate to a network of APUs.
Everything is going just as planned...