AMD CPU speculation... and expert conjecture

[esrever]

K12 is really exciting even tho its ARM, its the first AMD CPU built from the ground up since bulldozer, I hope it ends up good and maybe we would end up seeing some AMD based Android tablets.

The new x86 core is also very interesting, it does feel like it probably won't be a high end chip just because they are doing it along side the ARM core. I would be more inclined to believe it a replacement for jaguar where as puma+ seem to be a very small increment. There hasn't been any talks of excavator or beyond at all from AMD lately and I assume we would only get to hear about it when they fully announce their next APU.

 

[palladin9479]

K12 is really exciting even tho its ARM, its the first AMD CPU built from the ground up since bulldozer, I hope it ends up good and maybe we would end up seeing some AMD based Android tablets.

The new x86 core is also very interesting, it does feel like it probably won't be a high end chip just because they are doing it along side the ARM core. I would be more inclined to believe it a replacement for jaguar where as puma+ seem to be a very small increment. There hasn't been any talks of excavator or beyond at all from AMD lately and I assume we would only get to hear about it when they fully announce their next APU.

Their wording as a bit weird. It sounds like there will be two types of APUs that both fit the same socket. x86 + GCN for what current APU's do and ARM + GCN for ULP and embedded stuff. Of course servers will have their down implementations entirely. This is kind of interesting as the IBM PC BIOS doesn't allow for this, it would have to be an UEFI only solution. Mostly seems to be a costs savings tactic so MB designers don't need to produce multiple product lines.

he company didn’t offer much in the way of information but did tell us that this 64-bit ARMv8 CPU core will be in servers and embedded solutions along with semi-custom and ultra low power client devices.

 

[harly2]

K12 is really exciting even tho its ARM, its the first AMD CPU built from the ground up since bulldozer, I hope it ends up good and maybe we would end up seeing some AMD based Android tablets.

The new x86 core is also very interesting, it does feel like it probably won't be a high end chip just because they are doing it along side the ARM core. I would be more inclined to believe it a replacement for jaguar where as puma+ seem to be a very small increment. There hasn't been any talks of excavator or beyond at all from AMD lately and I assume we would only get to hear about it when they fully announce their next APU.

You don't feel it will be? well the conference today made it sound pretty high performance. It's clear to me that the BD core is dead, we now have full clarification that Jim Keller's team is designing an all new x86 core from the ground up along side the ARM core at the same time. My logic tells me the x86 core is likely big as the ARM core will be the efficient one. And both new cores are obviously FinFet, meaning the time frame for release is dependent on GloFlo. Good news is Puma+ and A57 fighting Intel at 20nm in 2015....should be good. Bad news is excavator in APU form will be fighting 14nm cores from Intel in 2015 in the mid-range and down for laptops/desktops.

 

[jdwii]

At the end of the day price/performance is all what matters and in this case your weak little Kaveri losses hard real hard. So again i ask you do you really want to do this?

I like the morphing of your pseudo-arguments The FUD started with Kaveri cannot hit 3Ghz due to bulk (your imagined friends at AMD said so). Then it changed to Kaveri is clocked at 3.7GHz due to bulk. Next it changed to show me a "production Kaveri @ 4.5GHz" or you will never accept that Kaveri can OC. Now it is changed to but but but but the price...

juanrga i'm also waiting for those benchmarks that shows the I5 2500K losing or even meeting a A10 Kaveri on average instead of a few benchmarks that show that

I see that you continue confused about this one.

yeah that was fun..so again i ask you for some kind of intelligent response or are people in spain incapable of this

 

[juanrga]

You don't call something that's been completely redesigned by some old name somewhat related to the project. And the link was perfectly valid because they're able to get another 40% performance advantage without even changing the underlying architecture. That's fairly significant for 1 generation, when they can also easily double the transistor count. Broadwell has 48 EU, so Skylake could easily go to 64 EU for the same power.

Your link continue being completely irrelevant to the Larrabee-like GPU on Skylake. Moreover, the CGPU projects are not about obtaining a performance advantage with current graphics; they are about something completely different.

 

[juanrga]

I see that you continue confused about this one.

yeah that was fun..so again i ask you for some kind of intelligent response or are people in spain incapable of this

Are you attacking Spaniards now because you cannot understand the BSN article?

 

[Cazalan]

You don't feel it will be? well the conference today made it sound pretty high performance. It's clear to me that the BD core is dead, we now have full clarification that Jim Keller's team is designing an all new x86 core from the ground up along side the ARM core at the same time. My logic tells me the x86 core is likely big as the ARM core will be the efficient one. And both new cores are obviously FinFet, meaning the time frame for release is dependent on GloFlo. Good news is Puma+ and A57 fighting Intel at 20nm in 2015....should be good. Bad news is excavator in APU form will be fighting 14nm cores from Intel in 2015 in the mid-range and down for laptops/desktops.

On the slides they still had x86 at the high end performance, and ARM at the lower end.

The comments about HSA were centered on the embedded/client APUs not the server APUs.

BD replacement in 2016. Such a long wait...

 

[etayorius]

So what is going to fill the HighEnd desktop segment till 2016? still the FX-8350 or more 4 Cores APUs?

 

[juanrga]

No data about the post-excavator x86 core is known at this time, except that it will be a 16 flop/core design and that is not CMT design. Probably it will be an SMT design (aka hyper-threading).

More data can be inferred about the K12 design. The A57 core has more IPC than Piledriver/Steamroller. The K12 design will be a custom core and will be competing against Denver/Cyclone and other custom cores.

The Denver core must be more or less so powerful like the Cyclone core, because

2x cyclone ~ 2x Denver ~ 4x A15.

The cyclone core is already Haswell class

http://www.extremetech.com/computing/179473-apples-a7-cyclone-cpu-detailed-a-desktop-class-chip-that-has-more-in-common-with-haswell-than-krait

and offers about 85% of Haswell IPC. Keller designed the cyclone core and is now designing the K12 core. In the most conservative case K12 would be so aggressive and wide as Cyclone, but would support higher frequencies. Keller explicitly mentioned this. By high-frequency I understand it will be clocked above 3GHz.

 

[juanrga]

So what is going to fill the HighEnd desktop segment till 2016? still the FX-8350 or more 4 Cores APUs?

Piledriver FX-series CPU extend up to 2015. Kaveri APU is replaced by Carrizo APU in 2015. Carrizo includes up to 4 Excavator cores.

 

[8350rocks]

No data about the post-excavator x86 core is known at this time, except that it will be a 16 flop/core design and that is not CMT design. Probably it will be an SMT design (aka hyper-threading).

More data can be inferred about the K12 design. The A57 core has more IPC than Piledriver/Steamroller. The K12 design will be a custom core and will be competing against Denver/Cyclone and other custom cores.

The Denver core must be more or less so powerful like the Cyclone core, because

2x cyclone ~ 2x Denver ~ 4x A15.

The cyclone core is already Haswell class

http://www.extremetech.com/computing/179473-apples-a7-cyclone-cpu-detailed-a-desktop-class-chip-that-has-more-in-common-with-haswell-than-krait

and offers about 85% of Haswell IPC. Keller designed the cyclone core and is now designing the K12 core. In the most conservative case K12 would be so aggressive and wide as Cyclone, but would support higher frequencies. Keller explicitly mentioned this. By high-frequency I understand it will be clocked above 3GHz.

Negative, I would find it an absurd change of course to go HTT. They may use a similar mechanic of some sort, or a redesigned CMT architecture, but I cannot see AMD going HTT, ever.

 

[juanrga]

Spoiler

No data about the post-excavator x86 core is known at this time, except that it will be a 16 flop/core design and that is not CMT design. Probably it will be an SMT design (aka hyper-threading).

More data can be inferred about the K12 design. The A57 core has more IPC than Piledriver/Steamroller. The K12 design will be a custom core and will be competing against Denver/Cyclone and other custom cores.

The Denver core must be more or less so powerful like the Cyclone core, because

2x cyclone ~ 2x Denver ~ 4x A15.

The cyclone core is already Haswell class

http://www.extremetech.com/computing/179473-apples-a7-cyclone-cpu-detailed-a-desktop-class-chip-that-has-more-in-common-with-haswell-than-krait

and offers about 85% of Haswell IPC. Keller designed the cyclone core and is now designing the K12 core. In the most conservative case K12 would be so aggressive and wide as Cyclone, but would support higher frequencies. Keller explicitly mentioned this. By high-frequency I understand it will be clocked above 3GHz.

Negative, I would find it an absurd change of course to go HTT. They may use a similar mechanic of some sort, or a redesigned CMT architecture, but I cannot see AMD going HTT, ever.

The current Bulldozer/Piledriver/Steamroller family already includes a partial implementation of SMT in each module.

I understand why you cannot see AMD doing a SMT desing. AMD has done just the contrary to each one of your predictions.

E.g. I said you about AMD plans to push ARM seriously because they know that ARM will win in the long run (I already explained why x86 will lose). Your reply was that ARM Seattle was only an "experiment" (your friend-at-AMD said so) and that only x86 was of the real interest for AMD... But once again your friend-at-AMD demonstrated that he has no idea.

This is from the recent AMD Conference:

I'm not quite sure whether the biggest news here is the announcement of a new high-end x86 architecture from AMD or the fact that ARMv8 is getting the same treatment.

Since we're talking about a replacement for Bulldozer, this is an entirely different class of beast from the "Puma+" and Cortex-A57 cores in the first SkyBridge parts. AMD's execs noted that these are high-frequency, high-performance CPU cores that will span the range from laptops to desktops to servers—and not just "microservers." We don't know exactly how big they'll be compared to Bulldozer or, say, Haswell. The smartest play might be to aim for something a little smaller than those cores, but that's the basic class of performance they're undoubtedly meant to achieve. AMD is returning to its roots, aiming to produce a best-in-class big core.

Well, two of them, this time.

AMD used the code-name "K12" to refer to the ARM core. I'm not clear yet whether that name also applies to the x86 core.

These two CPU microarchitectures will be, in the words of CTO Mark Papermaster, "sister cores." (Papermaster came to AMD from Apple, and he managed to lure CPU architect Jim Keller from Apple, too, shortly after Keller led the development of Apple's own 64-bit ARM core.) Keller explained during this morning's Q&A session that the new cores will share more than just pin compatibility. He said they will be "compatible at the pin level and inside." That likely means that the ARM and x86 SoCs based on these new cores will share the same internal plumbing—things like the I/O ring around the edges of the chip and the last-level cache. AMD's design teams will then be able to fit, say, four ARM cores or four x86 cores into the space on the interior section of the chip.

Presumably, these sister x86 and ARM cores will perform about the same, but they evidently are not just two variants of the same microarchitecture adapted to different ISAs. Keller was very complimentary about the ARMv8 ISA in his talk, saying it has more registers and "a proper three-operand instruction set." He noted that ARMv8 doesn't require the same instruction decoding hardware as an x86 processor, leaving more room to concentrate on performance. Keller even outright said that "the way we built ARM is a little different from x86" because it "has a bigger engine." I take that to mean AMD's ARM-compatible microarchitecture is somewhat wider than its sister, x86-compatible core. We'll have to see how that difference translates into performance in the long run.

Deep into the Q&A, some analysts were asking how AMD would differentiate itself from other contenders in the burgeoning ARM server space. Given what Keller and Papermaster shared, the answer seems quite obvious. If AMD were only offering A57-based parts like Seattle, it might have trouble standing out, but we're talking now about a full-fledged, next-generation processor worthy of the Opteron name. The other players in the ARM server space have, at least so far, concentrated almost exclusively on small, lower-power cores. Few have even made the transition to 64-bit addressing, and nothing in ARM's own portfolio of licensed cores is anywhere near this potent. The ARM-compatible K12 may be one of a kind if it arrives on schedule in 2016.

If it enables the folks building data centers to get the same sort of per-thread performance from ARM-based servers that they can from x86 processors, the K12 could obviate the need for x86 CPUs almost entirely. It could help key a dramatic transition from a single dominant ISA to two competing options—or it might even spark a longer transition away from the Intel-dominated x86 world to one ruled by the more open and expansive ARM ecosystem.

I am proud that my claims about ARM were rejected by 'experts' in this thread but real experts, such as AMD's Keller, are saying things very similar to those that I said here during months.

 

[8350rocks]

Juan, ARM will win in small devices...this is clear. Which is what was said to you many moons ago when you started all this mess.

x86 can do FAR too many things that would make life far more complicated for ARM to even bother with. Could ARM try? Sure...would they unseat x86 for this? Not very likely...perfect example is Windows RT. People will want windows on x86, why? Because it does all the things they want. Additionally...you will never get consumer Joe Q Public to switch his perfectly fine PC at home for some "new fangled" device just because a promo slide you showed by some speculator says ARM will win. He does not want to buy a new x86 rig to do what he wants better, so why would he abandon all that familiarity to go to something "untried" in the public PC sector? Are they fine with it in a tablet? Sure...would they trust their jobs and lives to it? Well, let us just say, FAR too many people are still on XP. The proof is in the pudding...ARM will not win anything that it is not already winning. I might add that x86 is already trying very flagrantly to steal market share as well.

I would argue, if x86 hardware competes at PPW for ULP devices...ARM dies a quick death. Look at the number of new tablets now that are running x86 compared to what was offered a year ago even. Then, consider many x86 devices can run android because it is linux, essentially, which means that the software would not have any issues adapting. That is all people really care about...will this play angry birds, and will it run android? If the answer is yes, then there is no concern from the public.

 

[Cazalan]

Your link continue being completely irrelevant to the Larrabee-like GPU on Skylake. Moreover, the CGPU projects are not about obtaining a performance advantage with current graphics; they are about something completely different.

That's hogwash as the roadmaps have already been shown with Skylake supporting GT2/GT3e/GT4e.

 

[juanrga]

"We have the world's best graphics. We know how to do high-frequency designs; we know how to do high-efficiency designs … We can extend the range that ARM's in - that’s a nice play for us" Jim Keller, AMD

This anecdote is very funny:

Of course, the ARM learning experience was still colored with a little competitiveness from the engineers with an x86 background, Keller admitted. "Our guys were so excited when they thought they’d found a bug in the ARM architecture using our tools," he said. "Turned out, it was a bug in our tools."

 

[juanrga]

Juan, ARM will win in small devices...this is clear. Which is what was said to you many moons ago when you started all this mess.

x86 can do FAR too many things that would make life far more complicated for ARM to even bother with.

You are repeating again the same nonsense RISC vs CISC*, and you aren't even reading what AMD's Papermaster and Keller are saying in the conference.

Please ignore this part also:

In the news posted by our very own Usman Pirzada, we detailed how AMD will be ditching their existing modular architecture and go for the Simultaneous Multi Threading (SMT) design.

[...]

With Jim Keller onboard, AMD is finally developing a new core architecture that’s built from scratch and means that AMD won’t make the same mistakes they made with Bulldozer. The architecture is still far from being ready and we are looking at a launch scenario of atleast 2016-2017 so that’s still a long time to go from where we are currently.

[...]

AMD’s 2015 line of APUs will stick with Excavator which will be the last modular AMD core before it hops onboard the SMT design.

* I already explained you that the first "C" in CISC doesn't mean "Complex", that any modern x86 CPU is implemented over RISC-like uops and that ARMv8 is a better ISA than x86-64.

 

[juanrga]

Your link continue being completely irrelevant to the Larrabee-like GPU on Skylake. Moreover, the CGPU projects are not about obtaining a performance advantage with current graphics; they are about something completely different.

That's hogwash as the roadmaps have already been shown with Skylake supporting GT2/GT3e/GT4e.

Those are generic labels that apply to different graphic architectures. What part of Intel claims that Skylake/posterior graphics are designed by the same architect that has designed the Phi is not still understood?

 

[Cazalan]

Those are generic labels that apply to different graphic architectures. What part of Intel claims that Skylake/posterior graphics are designed by the same architect that has designed the Phi is not still understood?

Oh right, my bad, I forgot the rule that when an engineer graduates they can only design 1 type of core for the rest of their life.

 

[jdwii]

i love juanrga if it wasn't for his far fetched comments i would have less enjoyment in my life its always nice to have such ridiculous statements in my life. Thank you juan

 

[colinp]

Another thing to note is that Carrizo is nowhere to be seen on AMD's updated roadmap. It goes from Kaveri, Beema, Mullins and Seattle in 2014 to Project Skybridge in 2015. No Excavator, no Carrizo anywhere.

With limited resources, it wouldn't surprise me if AMD has thrown all it's chips on the table (no pun intended) for Skybridge, canned Excavator, and at most we'll see a Kaveri refresh at some point to plug any gaps until Skybridge arrives, but not a full blown Excavator/Carrizo.

HEDT will only happen as a happy accident - a by product of Skybridge - not by design.

 

[gamerk316]

I'll wait for these new AMD x86 CPUs, my FX8350 does what I need it to do for now...

I think I'll definately hit the GPU upgrade cycle later this year though. I was wondering, any thoughts on this rumored 128bit Windows 9 OS? Would it be worth buying?

Oh, I just thought about this... what if AMD actually tracked this thread and bumped a couple of your guys ideas? Now wouldn't that be something? I'm curious to see what they're planning.

i don't think 64-bit is running out of steam any time soon. i read somewhere that 64-bit o.s. can address something-exabytes memory, so 128-bit addressing won't be helping with current tasks....

Nothing needs that much RAM. The two most RAM intensive tasks out there (DNA Molecule and Weather Simulation) don't even come close to needing that much addressing. Granted, you gain the benefit of being able to pump more data across at a single read, but you can do a larger memory bus independent of increasing addressing size. We'll never get close to reaching the full 16EB memory capability 64-bit gives us.

 

[gamerk316]

No data about the post-excavator x86 core is known at this time, except that it will be a 16 flop/core design and that is not CMT design. Probably it will be an SMT design (aka hyper-threading).

More data can be inferred about the K12 design. The A57 core has more IPC than Piledriver/Steamroller. The K12 design will be a custom core and will be competing against Denver/Cyclone and other custom cores.

The Denver core must be more or less so powerful like the Cyclone core, because

2x cyclone ~ 2x Denver ~ 4x A15.

The cyclone core is already Haswell class

http://www.extremetech.com/computing/179473-apples-a7-cyclone-cpu-detailed-a-desktop-class-chip-that-has-more-in-common-with-haswell-than-krait

and offers about 85% of Haswell IPC. Keller designed the cyclone core and is now designing the K12 core. In the most conservative case K12 would be so aggressive and wide as Cyclone, but would support higher frequencies. Keller explicitly mentioned this. By high-frequency I understand it will be clocked above 3GHz.

Negative, I would find it an absurd change of course to go HTT. They may use a similar mechanic of some sort, or a redesigned CMT architecture, but I cannot see AMD going HTT, ever.

There's plenty of ways to do SMT. HTT is the most known, CMT is another, and the Power arch does it a totally different way. We'll see.

* I already explained you that the first "C" in CISC doesn't mean "Complex", that any modern x86 CPU is implemented over RISC-like uops and that ARMv8 is a better ISA than x86-64.

I need to dig up the link, but a study a few years back on PURELY ISA performance showed ARM = X86 = PPC. Its the extra stuff on the CPU die that help in certain tasks that gives X86 its performance edge. Nothing is stopping ARM from adding those extra blocks, but then ARMs power profile goes out the window. But ISA isn't a huge factor in performance these days [its not like we code in assembly anymore], its the other blocks on the chip.

Those are generic labels that apply to different graphic architectures. What part of Intel claims that Skylake/posterior graphics are designed by the same architect that has designed the Phi is not still understood?

Which means sub-AMD APU level performance out of it. Using a few powerful cores is NOT how to make a GPU, but Intel hasn't gotten the memo yet. They don't know how to make weak cores, and it shows in their GPU designs.

Another thing to note is that Carrizo is nowhere to be seen on AMD's updated roadmap. It goes from Kaveri, Beema, Mullins and Seattle in 2014 to Project Skybridge in 2015. No Excavator, no Carrizo anywhere.

With limited resources, it wouldn't surprise me if AMD has thrown all it's chips on the table (no pun intended) for Skybridge, canned Excavator, and at most we'll see a Kaveri refresh at some point to plug any gaps until Skybridge arrives, but not a full blown Excavator/Carrizo.

HEDT will only happen as a happy accident - a by product of Skybridge - not by design.

but it makes sense for AMD: BD/PD has reached its evolutionary end, and at best, it reaches 2500k level performance. The arch was a poor decision, and I said it from the very beginning.

 

[juanrga]

Those are generic labels that apply to different graphic architectures. What part of Intel claims that Skylake/posterior graphics are designed by the same architect that has designed the Phi is not still understood?

Oh right, my bad, I forgot the rule that when an engineer graduates they can only design 1 type of core for the rest of their life.

Your rule explains why the Haswell/Broadwell graphics team was selected to design the next Phi... No, wait a different team did.

Have you considered PM Charlie to explain those rules? Have you considered to explain AMD that using your rules Koduri could design a CPU core and Keller a GPU core?

 

[juanrga]

There's plenty of ways to do SMT. HTT is the most known, CMT is another, and the Power arch does it a totally different way. We'll see.

In this slide the old AMD presented CMT as alternative to SMT

Spoiler

However, this slide is ignoring that the FPU of the CMT module is a SMT design, This is why I mentioned before that Bulldozer module already includes a partial implementation of SMT.

I need to dig up the link, but a study a few years back on PURELY ISA performance showed ARM = X86 = PPC. Its the extra stuff on the CPU die that help in certain tasks that gives X86 its performance edge. Nothing is stopping ARM from adding those extra blocks, but then ARMs power profile goes out the window. But ISA isn't a huge factor in performance these days [its not like we code in assembly anymore], its the other blocks on the chip.

During months I have emphasized in this thread that there is nothing magical in x86 that gives more performance than ARM or any other RISC ISA.

During this interesting conference Keller has remarked why ARM can offer more performance than x86. I already quoted his words. He is saying part of what I already said here during months. For instance, I already mentioned the x86 decoder performance penalty months ago.

Keller was very complimentary about the ARMv8 ISA having more registers. This is related to what I said about modern compiler optimizations months ago.

Keller has mentioned that the ARM core will have a "bigger engine" that the x86 core. I assume that the ARM core will be at least 6-wide (AMD FX are 4-wide).

Which means sub-AMD APU level performance out of it. Using a few powerful cores is NOT how to make a GPU, but Intel hasn't gotten the memo yet. They don't know how to make weak cores, and it shows in their GPU designs.

I agree on that a pure x86 cores approach would be less much powerful than ordinary GPU cores approach, but so far as I know the Intel approach will use modified x86 cores with some fixed graphics execution units that would be too costly (in performance terms) to replicate using x86.

The real advantage of this CGPU approach is on the flexibility and programmability.

In the end AMD, Nvidia and Intel are doing the same: blurring the line between traditional CPU cores and GPU cores.

BD/PD has reached its evolutionary end, and at best, it reaches 2500k level performance. The arch was a poor decision, and I said it from the very beginning.

Yeah Steamroller has caught 2500k level integer performance, but is still deficient in floating point (8 flops core vs 16 flops core). Presumably Excavator will correct that with the new 256-bit FMAC units.

AMD already admitted that the entire Bulldozer family is a failure. First it did the server head Feldman and this week the AMD president Rory Read.

Some fanboys would start to think on changing their forum nicknames

 

[juanrga]

Another thing to note is that Carrizo is nowhere to be seen on AMD's updated roadmap. It goes from Kaveri, Beema, Mullins and Seattle in 2014 to Project Skybridge in 2015. No Excavator, no Carrizo anywhere.

With limited resources, it wouldn't surprise me if AMD has thrown all it's chips on the table (no pun intended) for Skybridge, canned Excavator, and at most we'll see a Kaveri refresh at some point to plug any gaps until Skybridge arrives, but not a full blown Excavator/Carrizo.

Are you sure?

http://benchmarkhardware.com/images/stories/2014/Mayo/semana2/ADM-Roadmap-SkyBridge-BH.JPG