@8350rocks, the plans of AMD have not changed. The FF interconnect only provides 10Gbps per socket. This is slow even for future APU--APU communication. AMD exascale uses 40--100 Gbps interconnects for APU--APU.
FD-SOI doesn't scale well beyond 10nm, unlike FINFETs. Even IBM had rejected FD-SOI for its future nodes, but this doesn't matter anymore, with IBM abandoning the foundries business by due to the lack competitiveness.
Kaveri reduced clocks by two reasons: (i) lower TDP and (ii) HDL. FD-SOI was not in the menu because cannot provide the needed properties for GCN. AMD is not the only company that has rejected SOI. The foundry enginner correctly notices how all the big guys have rejected SOI due to being pure hype.
@gamerk316, Nvidia has not changed its plans, because the motivation to do CPU cores has not changed. When the project started out in 2006, it was an x86 core with Fermi GPU shaders. Due to x86 license problems, Nvidia changed to ARM cores and the GPU cores have been updated, but the main goal is unchanged. Nvidia has gave a technical talk about its plans for the 2018--2020. Check the slide that I reproduced a pair of pages ago. You can continue to negate evidence but dGPUs are replaced by HCNs (Heterogeneous Compute Nodes). Now check my signature.
@Cazalan, research follows a well-defined series of steps, starting with ideas in a piece of paper and following with computer simulations and finishig with prototypes on silicon. Exascale research doesn't even need drivers. No sure what are you arguing here.
@jdwii, only your comment was "silly", first because the FPU was integrated in the CPU despite being a big chip by the standards of the epoch
and, second, because at 14nm there is enough space for including a R9 290X on a small die APU. At 10nm there is double of that space.