AMD CPUs, SoC Rumors and Speculations Temp. thread 2

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The l4 is an excellent idea, I remember seeing a slide were a simulated trinity apu with hbm got up to 40% boost in CPU tasks, then there's iris broadwell which matches skylake in games with 4-500mhz less clock speed.
More ot I read today am4 will have 1331 pins, wonder why?
 


The simple thing I can think of is "passive" pin slots for future's sake. AMD has been around 940 pins since ~2005, so I would imagine they are running out of good layouts to have all the connectivity they need nowadays using the same socket (941 pins, I think).

In any case, I will imagine they'll keep the same strategy they have had with the current pin count. Just arrange them differently, but keep the socket pin count as close to the new number as possible.

Cheers!
 
HBM is a poor substitute for main memory, it's latency is too high and bus far too wide for consumer workloads. Current DDR3/DDR4 has better random access times then HBM, though HBM absolutely crush's it in total bandwidth. For this reason I suspect they will make APU's with 1~2 GB worth of HBM stacked on as dedicated graphics memory. The still have thermal issues to worry about but if Zen is as big an efficiency increase as they say, then they will run into the memory wall again.

EDRAM is really different then HBM. It's far more expensive per MB then HBM but has significantly faster access times, makes it ideal as a form of L4 cache. HBM is cheaper and has ridiculous bandwidth, so it's optimized for graphics processing.
 


HBM is a JEDEC replacement for GDDR5. Some low frequency APUs could use HBM as main memory, just as the PS4 APU uses GDDR5, but HBM will be not used as main RAM (neither as cache) for general APUs.

HMC (not from JEDEC) has been designed as replacement for both DDR3/4 and GDDR5.
 
Anything on comparisons in terms of IPC on Zen high end FX cpu's vs Skylake? I know they said 40% increase over last gen but I need to see that in action to believe it.
 
My stance: I'm assuming AMD is doing "best case" results here, though they claim they are getting a little better then they predicted. And as the details of the SMT implementation are unknown, it's hard to make a realistic estimate. I'd guesstimate 25-30% typical IPC gains in CPU bound tasks, with some tasks seeing upwards of 40-50%, before taking SMT into account. I also believe these gains will be offset by a lower clock speed, so I'd wager the CPU as a while, before factoring in the SMT implementation, will be about 20-25% faster per core.

Like always, once we get some more finite details and data, we can better guesstimate. The consensus guess however is Haswell/Broardwell level performance. The "worst case" is Ivy Bridge, the "best case" is Skylake. And I think that highlights the problem: Zen will likely be slower then Intels offerings at launch, and I can't see the chips being significantly marked down due to AMDs financial issues. We'll see I guess.
 
AMD's AM4 Platform Details Leaked: µOPGA Based Socket with 1331 Pins, 140W Max TDP
http://wccftech.com/amd-am4-%c2%b5opga-socket-1331/
AMD Zen 'Summit Ridge' CPUs and Intel 'Kaby Lake' CPUs Spotted in AIDA64 Changelog
http://wccftech.com/amd-zen-summit-ridge-cpus-intel-kaby-lake-cpus-spotted-aida64-changelog/
 
I've been looking around news for the new (i hope) chipset (northbridge and southbridge) along with the socket, but I can't find anything. Has anyone heard or read anything about it?

Mainly, I just want to know if they'll go the Intel way and cut the PCIe lanes or something. And if they will support a bazillion USB 3.1 ports 😛

Cheers!
 


Intel didn;t cut the PCIe lanes it is just that more I/O that runs off of PCIe was added into the platform. If AMD adopts all of those then their amount of available PCIe lanes will also drop as it is not cheap nor easy to have a ton of PCIe lanes. The more you have the more layers to the motherboard PCB and more chance of failure.

No details on the chipset yet and I doubt we will see any for at least another quarter or two.
 
I don't really know how to express it, but I meant it more in the X99 and Z170 kind of separation. I know they have said AM4 will be unified, but AMD is in a very volatile state, so I want some reassurance, haha. I don't know if that would even make an economical case to happen, but money talks.

And thanks for the link, 8350rocks (you'll be called ZenRocks next? lol).

Cheers!
 


I think I like Intels approach because it is a lot easier to have a cheaper board with dual channel than to try to make a cheaper board designed for quad channel. I really do not think that AMD nor Intel could make an all in one socket that can have all the features to support any CPU.

I will applaud AMD if they can because there are a lot of factors to consider that make it very hard to support a super high end CPU and a super low end CPU.
 
That is a fair point, jimmy. I forgot about that. PCIe is not everything that makes the X99 and Z170 different (as platforms, not only chipsets).

I am trying to see beyond the chosen amount of pins for the AM4 platform. That number has to mean something we're yet to find out. And given AMD's history, they might have learned something from the time they created the socket 754 and moved right away to 939 (base for the current ones). I want to know what they are hiding under that number, haha.

A wider HT BUS? 4 Channel DDR4? (one can dream, right?) 52 PCIe 3 lanes? What else could they chug into it before running into extreme costs? I mean, Intel already has 2K pins in the consumer sector and it is nice.

Sorry for rambling about it, but it is really intriguing me. Zen will be a thing, yes, but the platform will sustain the next gens to come, so they better do something interesting, right?

Cheers!
 
Well, much like you have the 970 and 990 class AM3+ boards...I am sure the chipsets will have different components.

I do know that there was, at one point, a 1050/1090 chipset developed a few years ago...nomenclature would likely be something similar to that. Though, I am sure the older chipsets will be ditched to incorporate DDR4 controller, etc.
 


Chipsets yes but whatever you design the board to do with the memory controller or PCIe then you are sort of stuck. If they are to have a unified platform then I doubt they will be adding, as Yuka mentioned, quad channel DDR4 to a low end board and I doubt they would only have high end boards with it for high end CPUs because even with the same socket it would create a mess and still separate the high and low end.

With two platforms it allowed Intel to do a staggered update cycle to offer more sooner in my opinion.

I am not against a unified platform I just think it will be much harder to pull off and that AMD will need to upgrade the entire platform a lot sooner.

We shall see.
 
I cannot be so sure...

I mean...look at the 970 boards versus the 990 boards. There are significant differences in PCI-e lanes between 970 and 990 boards. I could easily see an enthusiast and more casual sort of level on the boards.

Additionally, if they do MCMs, as was suggested by someone else...then...they could potentially have each 8 core package tied to 2 channels of memory, meaning if they did go to something like 16 cores, they could potentially have quad channel memory, just done some what differently.

The big thing here is, it will depend on how much of the SoC is actually on that die, and how much they can integrate separately into the board. There are clear advantages to both, it just remains to be completely seen what the actual approach ends up being.
 
^The MCM wouldn't work as if it has quad channel RAM then a dual channel RAM board would not work. In essence, it would still separate the two markets (enthusiast and high end) and the boards supporting quad channel RAM would cost well more than a high end dual channel RAM board.

As for the 970 vs the 990, if I remember correctly the chipset is what provides all the PCIe lanes unlike Intel which has some on thew CPU and some on the chipset. If Zen moves the primary PCIe lanes to the CPU the that will make it similar to Intel. Still in that case, it wont affect it as much but then a board that has more I/O than supported by a lower end CPU will have to disable it.
 
There is a simple economical advantage to have a unified consumer socket though: the underlying pin routing to whatever you want is always a "save" in terms of thumbing down features. Let me explain it a tad better: if you need dual instead of quad ch memory, then you just need to route less pins and have the CPU know/support that. I would imagine OEMs don't mind that way of doing it. They can re-use the same tooling for multiple products. That is how you see single dual boards and single quad boards, right? It will all depend on how AMD decides to design the CPU's integrated IMC and NorthBridge components and the main MoBo hub (SouthBridge). In that regard, I say 8350rocks is correct. I imagine Intel did not have a choice but to create the E line and X chipsets/platform to really get rid of the leftover inventory they had of CPUs that did not pass validation for the big OEMs. I don't think they though it would make perfect economical sense, to be honest. They just had to do it and, in a very Intel way, "make it work". Now, that is not saying the platform is bad or it doesn't have its place, but from a consumer ("prosumer" included), is not thaaaaat big of a thing. If you're serious about computing power houses, then you will go Xeon, right?

And I don't know how MCM works in practice for sockets, so I am not sure if it would or wouldn't make sense for a consumer CPU/APU. I mean that, other than just re-routing pins, MCM is not something so special that *any* socket/layout/MoBo could not use. Mixing MCM and regular monolithic CPUs in the same socket do sound bad though. I don't think AMD would do such thing.

Cheers!
 
http://www.bitsandchips.it/english/52-english-news/6811-first-zen-benchmarks-the-next-amd-uarch-is-a-major-step-forward

Wow...it appears that Zen performance is going to be so strong, Intel will actually go ahead and launch a 10 core Broadwell-E.

The CPU Hash (mostly FPU performance), for the 8 core zen shows to be stronger than a 20 core broadwell Xeon.

Meanwhile, the FMA implementation looks a tad bit suspect with the low ray trace scores...but I am not really concerned.

The ES shows base clock 3.0, which means we will likely see something around 3.5-3.7 all said and done on the top SKU before turbo.

If bits and chips is to be believed...this will be on par with broadwell-E in terms of per core performance...they even outright state so.

As a side note...that...is....actually, better than I had heard. I knew there was a lot of optimism about it. However...those numbers are stronger than I had even heard tossed around. Which is reassuring. Hopefully the other benchmarks that come out will reveal how much of the performance improvement this is across the board. If it is a legitimate 40%...it will likely be broadwell/skylake-ish performance...which would make it quite competitive. Especially if the cost is inline.
 
Those look interesting, although they don't tell the full story.

I still see the IMC is not that good, but at least is improved. And I'm trying to think on how to interpret the FP32 test in real world loads.

Anyway, never leave the salt too far from you until it actually launches, haha.

Cheers!
 
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