News AMD Details EPYC Bergamo CPUs with 128 Zen 4C Cores, Available Now

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AMD's Bergamo has 128 cores ... These chips will compete with Intel's 144-core Sierra Forest chips
Okay, so the headline on the live blog about "144-Core EPYC Bergamo" was just a mix up, then? I thought AMD had pulled a fast one!

Seemed plausible, as they could use 12 CCDs with 12 Zen 4c cores, each. We know the IO Die of EPYC can handle 12 CCDs, so it's not a big stretch to imagine.
 
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Okay, so the headline on the live blog about "144-Core EPYC Bergamo" was just a mix up, then? I thought AMD had pulled a fast one!

Seemed plausible, as they could use 12 CCDs with 12 Zen 4c cores, each. We know the IO Die of EPYC can handle 12 CCDs, so it's not a big stretch to imagine.
I would assume so. (I confirmed with Paul that it's 128-core and have updated that HL.) More importantly, a future 12 CCD variant with 192-cores should be possible. It's just not ready (or not needed?) yet.
 

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"AMD's 128-core EPYC Bergamo processors are the industry's first x86 could native CPUs, which are designed for the highest core density with an optimized Zen 4c core that halves the area needed for each core."

What the heck is that supposed to say?
 

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"AMD's 128-core EPYC Bergamo processors are the industry's first x86 could native CPUs, which are designed for the highest core density with an optimized Zen 4c core that halves the area needed for each core."

What the heck is that supposed to say?
I believe it should be cloud native CPUs instead of could native CPUs
 
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bit_user

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So it was 2:1 (ish)! That's a nice ratio for the dense/smol/concentrated/efficient/little/cucumber cores, for sure.
That must be including L3 cache, because the article then goes on to show the slide comparing the cores and states:

"AMD shared a few broad strokes about the Bergamo architecture, including that it has a core + L3 cache area of 2.48mm^2, which is 35% smaller than the 3.84mm^2"
 

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I would assume so. (I confirmed with Paul that it's 128-core and have updated that HL.) More importantly, a future 12 CCD variant with 192-cores should be possible. It's just not ready (or not needed?) yet.

I personally thought they will release the 192 core version already, but it could be for demand or some other technical difficulties.

Technical challenges I can think of it now:
1. Denser cores required denser traces in the interposer, they might need more time to engineer this.
2. The IO die doesn't have enough resources to handle 12x16C chiplets, they might need a new IO die for this.
3. Going beyond 128C will give very little benefits because of memory bandwidth limitations.
4. Power limitations means going beyond 128C means even lower clocks than now, making the benefits questionable.
5. A combination of above and other factors I missed.
 
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I personally thought they will release the 192 core version already, but it could be for demand or some other technical difficulties.

Technical challenges I can think of it now:
1. Denser cores required denser traces in the interposer, they might need more time to engineer this.
2. The IO die doesn't have enough resources to handle 12x16C chiplets, they might need a new IO die for this.
3. Going beyond 128C will give very little benefits because of memory bandwidth limitations.
4. Power limitations means going beyond 128C means even lower clocks than now, making the benefits questionable.
5. A combination of above and other factors I missed.
Power seems the most likely issue IMO. If it's hitting 360W with 128 cores and is already downclocked to stay within TDP, adding 50% more cores but clocking even lower would mean very diminished returns.
 

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I personally thought they will release the 192 core version already, but it could be for demand or some other technical difficulties.
The die shots show some different spacing between the CCDs than on Genoa, and the Bergamo CCDs look fatter. I wonder if there might be spatial constraints on where the CCDs are placed which keep them from packing them 3-across.
 
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