TeraMedia
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- Jan 26, 2006
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The pin count for an IB/Z77-equivalent set of outputs would be approximately 1155 + 942 - 48 (~6 pins per DMI lane * 4 lanes * 2 devices) = 2049. That's bigger than IB-E, but not infeasible. There might be an opportunity to save more pins by combining redundant power pins, laying out the used pins more efficiently (a lot are not used on the PCH at least), or eliminating legacy features such as PCI (about 40-50 pins) or moving them off-chip. And there may be a handful of other pins such as possibly CPU-Power-Good that wouldn't be needed since the signal would be on-chip. So it seems feasible to have a fully-integrated CPU/GPU/NB/SB, at least at mainstream levels of functionality and I/O bandwidth. Laptop APU/PCHs could further reduce pin count by reducing SATA, USB and PCIe connection count, perhaps eliminating another 50-100 pins.
Traditionally-chipset features such as v-Pro, RAID, HD Audio would need to be enabled by firmware rather than different SKUs, but it all seems doable. I imagine they would do it as two dies in a chip at first since the PCH uses a much cheaper fab process. They could even throw on a third die with 512-1024 MB of dedicated GDDR5 SD-RAM for the iGPU. But eventually the whole thing will be single-die when fab prices are low enough.
Traditionally-chipset features such as v-Pro, RAID, HD Audio would need to be enabled by firmware rather than different SKUs, but it all seems doable. I imagine they would do it as two dies in a chip at first since the PCH uses a much cheaper fab process. They could even throw on a third die with 512-1024 MB of dedicated GDDR5 SD-RAM for the iGPU. But eventually the whole thing will be single-die when fab prices are low enough.
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