AMD Piledriver rumours ... and expert conjecture

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We have had several requests for a sticky on AMD's yet to be released Piledriver architecture ... so here it is.

I want to make a few things clear though.

Post a question relevant to the topic, or information about the topic, or it will be deleted.

Post any negative personal comments about another user ... and they will be deleted.

Post flame baiting comments about the blue, red and green team and they will be deleted.

Enjoy ...
 


if a 3770K cannot beat a llano, then its is trite that a i3 3225 can't either.
 


It wasn't the gpu part that pissed me off, it was the CPU benchmarks part....utter nonsense....must have been drunk when they published it.

BTW, any news on die size? :) Wonder if it wud be larger than BD's, coz of all the inductors and capacitances they had to include for the RCM....plus each FPU has 2 extra MMX units.....or did they already start using those HD libraries for vishera's mask layout?
 
Look at toms review and every review seems to be getting at least 4.4Ghz out of it and when they Clock it their it does beat a I3 all the time and since its the same money i really don't think people should have to think much when their getting a A10 over a I3! Not to mention 1Ghz on the GPU is pretty amazing i'm gonna say you can get I3 Ivy performance and a 6670 performance for only 130$ if you overclock maybe throw in another 30$ for a decent heat-sink.
 

Considering trinity's die size compared to llano, the cpu portion is slightly smaller so I would think piledriver wouldn't be much larger, might be even smaller than bulldozer.
 


Dude, remember that llano used an entirely different core from BD/PD :) You definitely can't use that for a size comparison.
Any BD/PD module will definitely be smaller than two K10 based cores, that was part of the idea behind AMD's module approach in the first place; to get almost another core, for much less die space :)
 


But the power consumption against the i3 is enough to make a baby polar bear cry.
 
^^ you forget that trinity has moar transistors and moar cores than the core i3, that is why it uses moar powaa.

AMD’s Trinity Faces Off With Intel’s Ivy Bridge
http://semiaccurate.com/2012/10/01/amds-trinity-faces-off-with-intels-ivy-bridge/
stupid embargo games are stupid
http://semiaccurate.com/2012/10/01/amd-lets-us-tell-you-trinity-pricing/
 

Interesting, looks like the K parts are the leaky ones and the standard are more power friendly. the a10 5800k is 100W at 4.2 ghz while the 5700 is 4.0 ghz at 65W, same price.

would like to find some actual power comparisons between the two.

one binned for power, the other for performance.
 


If you're a power user, then you won't be touching Trinity (or an i3) with a barge pole.
 


The word out is AMD are going to use phase 1,2,3,4 for architectural evolution, that being BD to Excavator, the 2015 blueprint is the first high end X86-64 processor fused with a high end Radeon core, when that happens it could be the biggest game changer. Intel seem to be reaching the IPC wall where residual gains are made, but the future is not single instruction x86 computing and by the time Broadwell and whatever skylake or whatever other lake happens to be at 2015 could be distant in heterogeneous computing, the mantra "future is fusion" is basically correct, and I have stressed this enough AMD need to ensure by the time intel fathom entering this market they are over the hill and far away.

The article on toms a month or so back on "fusion" basically summed up AMD's approach, they will not tackle intel toe to toe on x86 level, its playing for what we are moving towards, right now they have the advantage its about ruthlessly exploiting it.
 
Thinking about the power difference between the A10 5800k and the A10 5700. I bet the efficiency comes from what trinity actually brought with it. RCM will have an ideal target frequency, and microscopic "flaws" will change the efficiency curve.

They aren't labeled HE because those were primarily slow speed chips.

Only problem I see with this is PD will be binned for efficiency for the server chips, DT only gets the "flawed" power hungry culled "overclockable" processors.

on the other hand, RCM once tweaked a bit should see some good power numbers on a more regular basis instead of just some of the cpus being binned for resonant clock mesh balance.
 
More on Steamroller based CPU's, as been touched on looks as though AMD have abandoned the single FPU approach, each core has its own frontside and FPU with allocated cache resources, that to me suggests de-unifying the cores giving two isolated cores per module, but the IPC yields should be high because of it.
 
The good thing I can see from all the reviews around is that Trinity is a genuine upgrade vs Llano on the CPU side - everyone already knew that the GPU would be an improvement.

So, what you're left with now is a choice between:

Intel if you want a faster CPU
Intel if you want a more efficient "APU"
AMD if you want the better GPU
AMD if you want a cheaper APU

And your choice will depend on your own usage patterns - there is no single answer that is right for everybody. Until the time that HSA is more prevalent, many users will be going for the solution that gives them the CPU uplift.

As for me, I'm still waiting for AMD to give me a compelling reason to upgrade from my 1055T, and I'm not sure, based on the Trinity reviews, that PD is going to be it. And I'm not sure if I'll wait until SR.
 

Hot_Chips_Steamroller_arch.png
http://semiaccurate.com/2012/09/06/a-brief-look-at-amds-steamroller-core/

If this is what your referring to, looks like there is still one fpu scheduler, but 2 decodes instead of the one. The main difference aside from that is the FP scheduler should be able to send the data to the gpu cores.

Not sure when the actual "fpu" will be only done by the gpu cores and eliminated from the "cpu" to be the true heterogeneous CPU that they are aiming for, excavator would be my guess. And with a discrete gpu, thats a lot of FPU potential, wich right now is the weakest performance in BD.

If they can just fix their cache latency to be closer to what Intel has ...
 


PD is a feasible update to your chip, but its more prudent to wait until SR, if Bulldozer was phase 1 of module architecture, PD is phase 1.1, SR is modular architecture phase 2 and completely different to current architectures. It was a gamble that AMD took which hasn't really delivered the kind of performance hoped for.
 


PD has tweaked cache latencies, further tweaks for SR.

I think the issue of HSA, I am certain from what has been said that AMD will only be looking at that after excavator, that means evolving the architecture until 2014 thereafter the next roadmap will be a true HSA roadmap with 2015 and 2016 architectures TBA.

Ditto on the decoders, I am going through to many _PU's today.
 
^
they were like this
pd/trinity will be equal/near to phenom/k10 in performance per ghz
and more clockable thus better per core performance
but due to performace loss in a module , 4ghz module will be equal/near to 3.2ghz 2xk10 cores in multithreaded

and thus 8350 looks like 20-25 % better than 1090t and 8150 in multithreaded
and ~10% better than 1090t in single thread
everything at stock, with marginal error in prediction 😛 😀
 


Interesting - according to the article AMD's Q3 doesn't look like it's going to be good. Stock dropped to $3.28 yesterday, no guidance from AMD that I could see, so I expect it'll have another big drop after the earnings report..

Also according to AT's benchmarks single-thread performance on the A10 seems to be around 6% better than Bulldozer, at least on Cinebench - thought it was going to be a 15% improvement??

50397.png
 
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