Power requirements are based on what is needed to keep the thing working at spec.
Consider a cpu, it’s a huge current sink, 88W at 1V (nominal value for voltage) is an 88A draw. Many tiny transistors switching up to 5.4 billion times a second requires precise timing and granular power control.
Efficiency and power reduction
As the power is decreased the ability of a transistor to get to logic 1 is diminished. There is a rise time, logic 1/rise time gives you the slew rate. The slew rate for a particular chip can be found on its datasheet. With regard to CPUs the slew rate for a block of logic is accounted for at design time. Given a known rise time for the transistors on the silicon in those CPUs a supply voltage range is specified with tolerances for minima and to stop it burning up, maxima. Outside of the tolerances there is a grey area where the chips will still function but the performance may be degraded/unstable in the case of low voltage or simply head towards burning out in the case of high voltages.
If you reduce power
Power is volts x amps or power is amps squared x r
where r is the cpu resistance
Reducing power reduces the ability of the processor to maintain the slew rate, as the current draw is restricted by reducing the power then at a point the voltage supply, the push, will reduce as you are trying to draw more than the psu (vrm) is configured to supply.
If you reduce power within the design limits then yes, you can be more efficient to some extent. Reducing power can restrict the speed to which the cpu will clock. Good silicon, good transistors will switch to a higher speed than bad so good silicon at lower power will maintain a high(er) clock rate. Poorer quality silicon will fail, it won’t be able to switch fast enough (slew rate).
Overclocking without increasing power pushes the CPU into the “low power” state, the transistors cannot switch to logic 1 in time and a fault is seen. The solution is to increase the power giving a bigger voltage push. The drawback is that the switching can create a ringing which must settle, it’s all a balance, slew rate + ringing = settling time. The ringing is exacerbated by higher voltages.
Efficiency by reducing power supply can be enhanced to a point, that being the least good transistor failing, falling out of tolerance and not switching in time. The specs published for a device have a tolerance, psu A != psu B
If you stay within the tolerances chances are that you will be fine in normal use, under volted and under powered but when you update your bios, reset to defaults before doing so.