News AMD Ryzen 7 5800X Emerges As A Serious Rival For The Intel Core i9-10900K

[GetSmart]

Main question is... How reliable is "CPU framerate" to determine the performance of a particular CPU? 🤔

Another example, source https://www.ashesofthesingularity.c...k-result/31a32c94-d43f-4924-ab2a-ccfb43451beb 😉

This one also with 32GB memory.

 

[CerianK]

CPU framerate seems to be memory bandwidth sensitive. Perhaps that AMD Ryzen 7 5800X was using DDR5 memory? 🤔

I thought about that already, but realized that it is unlikely since DDR5 would require a different socket to handle an updated memory controller on the CPU. The only leaks on such a thing are for mobile using LPDDR5 (where socket compatibility is not required).

 

[GetSmart]

I thought about that already, but realized that it is unlikely since DDR5 would require a different socket to handle an updated memory controller on the CPU. The only leaks on such a thing are for mobile using LPDDR5 (where socket compatibility is not required).

AMD's next generation CPUs may have dual DDR4 and DDR5 memory controllers for either AM4 or AM5 socket. For speculation, this one could be running on a yet to be seen future AM5 socket... 😉

 

[CerianK]

AMD's next generation CPUs may have dual DDR4 and DDR5 memory controllers for either AM4 or AM5 socket. For speculation, this one could be running on a yet to be seen future AM5 socket... 😉

That would be spectacular (and devastating to Intel)... but I am not going to hold my breath (for a week).

 

[McGaz]

I've been wondering about an upgrade for before Zen 2 came out. It wasn't a big enough improvement for me, so I thought I'd hold out for the next gen. So, I've been squirreling money away for some time and I'm now hoping to go for a 3080 and a 5090X... it's all getting quite exciting now

 

[digitalgriffin]

Even many of the 3000 series have escalated rapidly in price, particularly on the lower end. The 3600, for instance, has risen from $155 to $205, in little over a month.

You know the rules of free market: Supply and Demand

If AMD shifted production from 3600->XBOX/PS/Zen3 CPU's months ago this would explain it. Supply went down to price went up. It takes a while to switch over production. It's not like one day you can produce "X", switch a lithography mask and then produce "Y". It takes longer than that after calibration and test runs. I think over a week or two. So that's down time you plan for in advance.

 

[digitalgriffin]

I don't disagree. I'm interested to see how the CCX and IF changes improve performance across the board. Streamlining the process of communication could only help speed things up, but I have to wonder why it's taken this long to make such a dramatic change? One would think that AMD would have known about this prior to Z2 and make the changes then rather than wait until now unless there was something in the architecture itself which prohibited it. I suppose we'll see just how marked an improvement this is soon enough.

No matter what, we're benefiting from it and I can't wait to build a new rig. I've greatly enjoyed my FX8350 and have never felt disappointed but this is going to be a whole new ballgame for me and others like me who have waited to reap the rewards.

Multi CPU cache coherency requires LOTS of circuits. I mean LOTS of circuits. It often has to be timed to deal with issues like deadlocks and timing. Let me show you why.

Lets say CPU 1 CCX 1 and CPU 4 CCX 2 are running on the same memory processing it.

CPU1 writes a new value for memory location 0xABCD. That immediately goes to cache layer level 1. Cache layer level 2 and level 3 tables are checked at the same time to see if the cache page for that section of memory needs to be marked as dirty. CPU1 then releases the thread lock for that section of memory (designed to prevent race conditions)

CPU4 however is now reading from the same memory at the same time 0xABCD was written to by CPU1. (Race condition is cache based) The thread lock was released so it assumes it's safe to work on the same section of memory. But IF it's retrieving from it's local cache (CPU 4 L2/L1), and it wasn't properly updated as dirty in time, you're squicked.

Writing an efficient Level 3 cache system is tricky when dealing with so many cores. The # of circuits grows exponentially with each core. n*(n-1) connections. The scheduler can look ahead and try to predict ahead of time when 0xABCD is written too and notify the Infinity cache early. But it's not a guarantee. If you do a random memory injection to simulate something like noise (Poisson distribution) memory access may be chaotic. So predicting it ahead of time is difficult.


Side note: Computer system architectures was one of my favorite courses in college.

 

[InvalidError]

AMD's next generation CPUs may have dual DDR4 and DDR5 memory controllers for either AM4 or AM5 socket. For speculation, this one could be running on a yet to be seen future AM5 socket... 😉

They don't have separate memory controllers for DDR4 and DDR5, they have one memory controller and a thin layer that handles the differences in MAC/PHY details.

 

[GetSmart]

They don't have separate memory controllers for DDR4 and DDR5, they have one memory controller and a thin layer that handles the differences in MAC/PHY details.

Some of AMD's previous CPUs have dual memory controllers (like some AM3 CPUs can be used on AM2+ motherboards). Heck even many of the mobile SoCs nowadays have memory controllers to handle between LPDDR3, DDR4 or LPDDR4X memory.

 

[InvalidError]

Some of AMD's previous CPUs have dual memory controllers (like some AM3 CPUs can be used on AM2+ motherboards). Heck even many of the mobile SoCs nowadays have memory controllers to handle between LPDDR3, DDR4 or LPDDR4X memory.

A single memory controller can support multiple memory standards, all you need is a few muxes to handle pins that change purposes between standards and IO drivers that can handle the different voltages, bus driver, equalization and termination schemes. The logic that drives overall DRAM operation hasn't fundamentally changed since DRAM was invented, so there is no point in duplicating the memory controller just because a few pins have been re-arranged a little such as dedicated RAS, CAS, etc. lines getting replaced by command words, merely a more pin-efficient representation of the same things.

Design a memory controller for the most advanced memory standard you want to support and you have practically all the bits and bobs necessary to support all older generations in its lineage with little more than a few LUTs.

 

[Zerk2012]

I think I'll judge when real benchmarks and prices are out.

I just upgraded so don't matter to me till about 5 years from now.

 

[SkyBill40]

Multi CPU cache coherency requires LOTS of circuits. I mean LOTS of circuits. It often has to be timed to deal with issues like deadlocks and timing. Let me show you why.

Lets say CPU 1 CCX 1 and CPU 4 CCX 2 are running on the same memory processing it.

snip

While system architecture isn't my forte but would seem to be something you deeply enjoy, I get what you're saying. Thanks for the detailed explanation as things like that are beneficial as both a learning experience and general knowledge.

 

[CerianK]

DDR4 and DDR5 signaling are so substantially different (at both ends of the path) that I think it would be too risky to introduce additional gating to support both on the same memory controller, as that would substantially increase the design time investment, and potentially limit the upper end speed for overclocking/stability headroom.

 

[InvalidError]

DDR4 and DDR5 signaling are so substantially different

Not really that different: DIMMs got split into two independent channels and commands/addresses are being muxed on a faster narrower command/address bus which now requires the same attention to signal integrity as the data pins.

The real challenge of pushing higher speeds is signal integrity from the IO pins to the DRAM/RCD/DB, not the memory controller.

 

[cryoburner]

AMD's next generation CPUs may have dual DDR4 and DDR5 memory controllers for either AM4 or AM5 socket. For speculation, this one could be running on a yet to be seen future AM5 socket...

This seems pretty unlikely. These are the processors AMD is expected to be announcing next week, and I don't believe there have yet been any leaks suggesting a new generation of motherboards will be launching alongside these CPUs. And while the DDR5 specification may have been finalized a few months back, DDR5 modules probably won't be available at retail for a while still. The new RAM may also not provide much benefit at launch either. If prior launches of new RAM standards are anything to go by, the modules initially available will likely not be appreciably faster than what's available with DDR4, but they will cost a fair amount more. A leaked roadmap from AMD earlier this year suggested DDR5 support would not be coming until 2022, and that seems fairly likely, and I would not expect a new socket before then.

 

[InvalidError]

The new RAM may also not provide much benefit at launch either.

DDR5 is expected to launch at 4800MT/s baseline with each DIMM split into two channels, so I'd expect the ~20% increase in bandwidth over premium DDR4 and doubling of access concurrency to yield a decent boost once the price premium for DDR5 CPU+motherboard+RAM become palatable. The main problem with most previous DDR generation is that by the time next-gen launched, affordable previous-gen memory was already well into next-gen at-launch OC territory. I don't expect DDR4-4800 to get affordable any time soon if ever, so there is plenty of margin between mainstream DDR4-3200-3600 and the premium stuff to accommodate DDR5's costs.

For the first year or two though, the price premium will likely be too steep for people to bother regardless of how good DDR5 may turn out.

 

[GetSmart]

Not really that different: DIMMs got split into two independent channels and commands/addresses are being muxed on a faster narrower command/address bus which now requires the same attention to signal integrity as the data pins.

The real challenge of pushing higher speeds is signal integrity from the IO pins to the DRAM/RCD/DB, not the memory controller.

The signalling voltages are also different. Additionally the address page access method is also different. Thus its not simply a matter just simply multiplexing logic routes. DDR5 may require a different controller. 🤓

And in the news, SK Hynix launches first DDR5 memory https://www.prnewswire.com/news-releases/sk-hynix-launches-worlds-first-ddr5-dram-301146087.html 🇰🇷

 

[InvalidError]

The signalling voltages are also different. Additionally the address page access method is also different. Thus its not simply a matter just simply multiplexing logic routes. DDR5 may require a different controller. 🤓

Signaling voltages are no big deal, only need to build the drivers/receivers to work at the lower voltage and the rest is just a matter of changing reference voltages and it is already done by LPDDR4. Most of the changes from DDR4 to DDR5 were already part of LPDDR4 too.