Amd Ryzen Threadripper & X399 MegaThread! FAQ & Resources

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aldaia

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The dies are probably failed dies reused as dummies and nothing else. But juanrga likes conspiracy theories.
 

aldaia

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You contradict yourself, just a few days ago you said in RWT forum
The roadmap is

· Zen on 14nm (2017)
· Zen on 14nm+ (2018)
· Zen2 on 7nm (2019)
· Zen3 on 7nm+ (2020?)
That, or there is someone else named juanrga in RWT :D
 

juanrga

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There is no conspiracy, just another case of blatant lie from AMD.

der8auer delidded an ES and found four pieces looking as dies. AMD replied officially that there are only two ZP dies in TR, and that the other two pieces are blanks to help structural stability. AMD pretended that TR aren't failed EPYCs. AMD also requested the original delidding video to be taken down.

der8auer didn't believe the official statement, just purchased a retail TR chip, delidded it, cleaned the pieces, and found there are four ZP dies in TR. There is no blanks. TR are failed EPYCs.
 

juanrga

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One juanrga talks about Zen. The other juanrga talks about Zen2. So there is no contradiction.
 

aldaia

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Lol, your (conspiracy) theory does not hold at all, but it shows how little you know about sockets (or the extend of your hatred towards AMD). There are many technical reasons why it's impossible to reuse failed EPYCS into TRs, several sites and some knowledgeable people already debunked the failed EPYC conspiracy.

Besides technical reasons there is commonsense. Of those two options:
a) Spend money cutting pieces the size of a die to be put in TR, and spend more money to dispose of the ZP failed dies.
b) "recycle" failed ZP dies as dummies to help structural stability and save money twice.

Commonsense dictates b) and therefore AMD didn't lie, you think it's a), enough said.

Cheers.



 

aldaia

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It was obvious from the context that the person you where answering was referring to Zen2, but anyway, whatever you say.

 

juanrga

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What conspiracy? We are simply mentioning the obvious possibility that ThreadRipper are failed EPYCs. Meanwhile Tomshardware has just published an article on the topic: It's possible that the Threadripper processors are simply EPYC processors with die that weren't successfully mated to the substrate.



It is not about what I think or I don't. It is about what AMD said about TR and how der8hauer has demonstrated it wasn't true.
 

juanrga

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He wrote "Zen" and I replied to what he wrote. Even if he had written "Zen2" instead, what he wrote continues being incorrect.
 

aldaia

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Can you post a link to what AMD said? Because as far as I know they said there where two dummy dies. No lies in there. And who cares if the dummies are plastic, failed dies or a piece of ivory?

Regarding TR being failed EPYCs you totally wrong and it has already been demonstrated to you in other forums.
juanrga (noemail.delete@this.juanrga.com) on September 16, 2017 4:47 am wrote:
> Well, this alternative explanation isn't true. AMD lied about what is inside Threadripper.
> There are four dies in ThreadRipper. The CPUs are failed EPYCs.
>
> https://www.eteknix.com/threadripper-not-contain-dummy-dies/
>
The packages are physically different, anyone saying that a Threadripper is a failed Epyc is a rank idiot. If I need to explain this in more detail, consider yourself in the rank idiot category.

-Charlie
I fail to understand why you insist here, but i suspect Charlie is right in every single word he wrote.
 

juanrga

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AMD specified to the press, including der8hauer, that those spacers were "blanks", not actual dies, as reported then in the news:

Update: AMD has clarified that two of the four silicon die are 'dummy' blanks rather than disabled Ryzen chips. They are included for structural stability. The two die that are enabled sit diagonally from each other to aid in cooling.
Der8hauer didn't believe the official explanation and tested it by himself:

How far would you go to prove a point? Well, the overclocker and CPU delidding expert der8auer has decided to put AMD's "Dummy Dies" claim to the test, to find out once and for all whether or not AMD is using failed/defective Ryzen dies or silicon spacers.
Thanks to him we now know there are four zeppelin dies on ThreadRipper: two dies enabled and two dies disabled. AMD lied when said that there is no disabled dies on ThreadRipper. I fail to see why you insist on negating facts.

I just asked Charlie which are the differences in the packages. Waiting his answer... I am not sure which is his misconception here, but it is evident that the possibility that ThredRipper are failed EPYCs is real, as mentioned in the recent Tomshardware article linked above.
 


Relevant to the discussion: https://en.wikipedia.org/wiki/Blank_(cartridge)

/popcorn
 

aldaia

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What you say about AMD's words is Irrelevant, you are not quoting AMD, those are not AMD words, but the press words. Here are other quotes from the press:
When we asked AMD about this at a recent summit they claimed that Threadripper has two working dies and two dummies to get you to the 16-cores. The two dummies would be in place for better structural support.
No specifics about what material is used for dummies, could be anything, including failed dies, as Charlie has already confirmed to you:
AMD said to me that they are there for mechanical support and thermal reason, they are non-functional spacers. They never specified what they are made from, just that they are NOT good die.
Disabled is not the same as non-functioning. Der8hauer did not 'prove' anything was disabled, just that the mechanical spacers were made from non-working dies.


He has no misconception, ThreadRipper package is electrically different from Epyc, the possibility that ThreadRippers are failed EPYCs is excactly zero. If instead of trolling in all AMD related forums, trying to prove your point about how evil AMD is, you devoted 5 minutes to think about it you will realize that too. As for Charlie's answer, I think he already answered you:
The packages are physically different, anyone saying that a Threadripper is a failed Epyc is a rank idiot. If I need to explain this in more detail, consider yourself in the rank idiot category.

-Charlie
 

goldstone77

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Think about this clearly, the dies are already binned, and sorted. They just don't Willy Nilly dies into packages. They know what they are before they go into the package. The insight is what most people expected when De8uer Der8auer delidded a Threadripper engineering sample and found that the processors still feature all four Zeppelin die to begin with. There will be a 32 core ThreadRipper! Intel's entire pricing schemes are being devastated by AMD's innovation is the take away from all this. Who cares if they used dead dies for dummies.

wil·ly-nil·ly
1.
whether one likes it or not.
2.
without direction or planning; haphazardly
 

juanrga

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As mentioned above, AMD said to the press that TR has only two dies:

AMD has clarified that two of the four silicon die are 'dummy' blanks rather than disabled Ryzen chips.
That is the reason why the press published, then, that there are only two dies. der8hauer didn't trust AMD official statement and decided to test by himself if what AMD was saying the truth or was lying:

How far would you go to prove a point? Well, the overclocker and CPU delidding expert der8auer has decided to put AMD's "Dummy Dies" claim to the test, to find out once and for all whether or not AMD is using failed/defective Ryzen dies or silicon spacers.
He found that AMD lied. There are four Zeppelin dies on ThreadRipper.

Charlie has changed the version. In his original post in the older thread "ThreadRipper is four dies (!), two dies are unused (?!?!)" he wrote that AMD said him that ThreadRipper has only two dies:

There are only 2 dies and the package is electrically different from Naples/Epyc, it isn't a salvage part. I will write it up in a bit but the 'rumors' are BS and based on both ignorance and, well, not asking the source.

-Charlie
Now der8hauer has demonstrated that there are four dies, despite Charlie insults. I am still awaiting to Charlie to detail the packages differences.
 

juanrga

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I say there is no 32-core ThreadRipper, because thermals limits of the socket and other stuff like quad-channel. And what "AMD's innovation" do you mean? Moar cores and MCM packages are older technologies not invented by AMD.
 

8350rocks

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Interesting, since it is already in the process of taping out on 7nm...
 

8350rocks

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Intel is going to use MCM after their monolithic die run this time around...just FYI. They are also going MOAR CORZ...
 

juanrga

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Don't confound Zen with Zen2.



Intel isn't going to use MCM. Moreover who is using what is irrelevant to the point made. The point was that using MCM is not innovating, because MCM is an older technology has been used for decades. Don't pretend AMD is inventing the wheel.

And yes, Intel is also going for moar cores, but the difference here is that no Intel fanboy calls that "innovation".
 

goldstone77

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Stop being obtuse Juanrga... Zen(Zen2; Zen3; 7nm; 7nm+) Zen being the underlying uArch behind the design with enhancements.
 

goldstone77

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Offering more performance for less money! Performance that was previously much more expensive! That is innovation!
 

juanrga

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It is about being precise and using the proper terminology. Zen, Zen2, and Zen3 are different microarchitectures

 

juanrga

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Offering more performance for less money is like the whole industry advances. IBM, Intel, AMD, Nvidia, Apple, Sun, ARM, Qualcomm,... all them offer new products with more performace for less money; otherwise people wouldn't upgrade. There is no "AMD's innovation" here.
 

goldstone77

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You are just being argumentative. AMD has the lead in price to performance.
 

juanrga

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I am explaining how things are. Price is not a linear function of performance:


  • ■ IPC is not a linear function of number of transistors. Thus getting 10% higher IPC doesn't cost 10% more.
    ■ 512bit FMAC units and datapaths require much more transistors than 256bit or 128bit, and that extra space adds to the cost, but that extra cost is not counted when reviews only check performance serial x86 workloads or 128bit vector code, which don't use the 512bit.
    ■ Yields aren't linear. So dies with higher core counts cost much more than dies with lower core count. That is the reason why AMD uses a MCM approach instead a monolithic die. A pair of 8-core dies is cheaper than a single 16-core die.
    ■ I know that developing a process node that can hit 5GHz costs much more than developing a process node that can hit 4GHz.
    ■ I know that developing a process node with HD cell density of 0.0499μm² costs much more than developing a process node with 0.064μm² density.
Summing all those factors, we find that the CPU that targets higher performance will cost much more and will have a lower performance/price ratio that the CPU that targets lower performance. And all that without even considering production volumes. Mainstream products fabricated in larger volumes are cheaper than enthusiast products fabricated in low volume, as follows from a simple application of economic laws of scale and serial fabrication.

That is why Intel charges more for its chips than AMD. Some of the above reasons are also the reason why AMD charges $500 for the 1800X and $300 for the 1700, despite both are same microarchitecture, same core count, same die, same process node...

The nonlinear relation between price and performance also applies to opther industries. Developing a car can hit 400KM/h cost much much more than developing a car that only hits 200Km/h. So when comparing speed/price a Toyota Prius wins over a Ferrari F150. The Ferrari has worse performance/price ratio because the laws of physics aren't linear, not because Ferrari is an evil company and Toyota is "innovating".

Same applies to Intel vs AMD. The same applies to motherboard companies, same applies to phone companies, same applies to houses companies...

People would stop pretending that AMD leadership on performance/price is something special, or revolutionary or "innovative". It is not. It is just the result of a lower performance target technology.

I can sure you that if AMD ported RyZen to Glofo 14HP node, added two extra cores per die, and updated to 512bit, the resulting chips wouldn't cost much much more and ruin the performance/price ratio.
 


Interesting you mention, so blatantly as well, that "Toyota is not being innovative" compared to Ferrari. Toyota is bigger (as a company) than Ferrari (as an individual brand and not under the FCA umbrella, but even then, they might be bigger anyway). I actually have to say it is absolutely the other way around. Ferrari is the company that doesn't innovate and sticks to "old formulas that work". Hell, they even don't like using Turbos in their engines and we all know they catch fire easily, whereas we all know Toyotas are going to outlive humanity and will be driven by the mutant cockroaches after humanity dies. In terms of "pure" innovation, Toyota has more under their belt than the whole of FCA's divisions combined. Just take a look at the first companies to use VVT and the first companies to use Direct Injection, Dual Headcams, 16 valves, etc.. You will find Toyota being the first in all of them, pretty much.

Ironically enough, I do agree that in your analogy, Intel fits Ferrari better. They sell you the illusion of buying a great car, great performance, but never telling you about running costs and how often it will break on you, or even burn to the ground. Toyota will sell you, pretty much, anything you want in pretty much any price bracket and you will be counting on their innovations day in and day out. Ferrari will give you a great illusion of going faster, great track numbers and a lot epeen, but at the end of the day, if you buy a Toyota LFA or even a Toyobaru, you will have the same fun, or even more.

But hey! Let's not get the analogy get in the way of bashing AMD's simple approach to solving complex problems that end up being good for everyone.

EDIT: About that "TR is a lie!" topic: https://twitter.com/IanCutress/status/909627789669781504
 
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