AMD Athlon 64 (Greyhound) is expected to be released in H1 2008 on a 65nm process. Greyhound is expected to be the first K8L based CPU, featuring 4 cores. Each core will feature 64KB - 32KB Instruction, 32KB Data - of L1 (down from 128KB in the K8 architecture), 512KB of L2 cache per core and - in it's Opteron form, 2MB of shared L3 cache. K8L will also feature AMD's DICE (Dynamic Independent Core Engagement) power saving technology which enables each core to alter it's own p-state (Power state) right down to putting a core in a full Halt condition and will introduce HyperTransport 3. Hypertransport 3 will introduce a number of improvements. Firstly, the HT speed will be increased to 2.6Ghz, which will allow for 5.2GT/s, compared with a maximum of 1.4Ghz in HT2 (1Ghz in the K8 architecture). Secondly HT3 will introduce 'Un Ganging', which will allow either one 16-bit link or two 8-bit links to be created on the fly. This will be particularly useful with multi-socket Opteron servers as it can allow for single memory hop access to memory which would previously have taken two hops. Additionally the K8L core will have an enhanced instruction set, Indirect branch prediction, 32-byte prefetch (compared with 16 in the K8 architecture), 48-bit addressing with 1GB pages, better cache coherency, I/O virtualisation, Memory mirroring, data poisoning and HT retry protocol support, and 2x128-bit SSE units (compared with 2x64-bit units in K8) featuring support for single cycle 128-bit instructions. Greyhound will interface to DDR2 memory, with the K8L core featuring support for FBD and, in a future memory controller revision, DDR3 and FBD2 support.