First of all the use of silicon interposers (instead of the flipchip method for which Intel holds several patents) in multi-die packaging is an evolution, not a revolution and certainly doesn’t warrant someone a claim over the entire MCM concept as AMD’s fbs have done (who even say that anyone that uses MCM is copying AMD).
And
here is an Anandtech article from back in 2006 saying this about Intel’s flipchip MCM approach:
“We've shown in the past that there's no real-world performance penalty to this approach to manufacturing, and there are numerous benefits from Intel's perspective. Yields are improved by producing a two die quad-core processor rather than a single die. The approach also improves manufacturing flexibility since Intel can decide at a very late stage whether to produce a dual or quad core processor after a die is fabbed.”
And
here is an article before that:
“While having two independent dual-core die isn't as fast as a single integrated quad-core die, we expect the performance penalty to be minimal in most applications (just as it was with the first dual core Intel chips). There are some benefits to using two independent dual-core die on a single package, which are highlighted above. They mostly relate to manufacturing and optimizing costs/production and thus won't be directly visible to the end user. If history repeats itself, we should expect Penryn (45nm) to be Intel's first single die quad-core desktop processor.”
So apparently, at the time, flipchip was more than enough for MCM - so why increase the cost with a silicon interposer?
Besides it was not AMD that was first to use silicon interposers anyway. The concept has existed since the 1990s. Micro Module Systems (a DEC spin-off) was amongst the first to use it commercially. From the major silicon providers, Xilinx was the first to use it commercially in 2011 (see
here) in its FPGAs.
More importantly, in the same year (2011) Intel was already publishing about EMIB (see
here),
which is a superior implementation of the 2.5D packaging concept as it avoids the use of TSVs (which are associated with several issues and limitations). In 2015, EMIB was incorporated to their FPGAs (Stratix 10, see
here) – it was one of the reasons Altera partnered with Intel as their foundry before they finally got acquired by Intel.
No that happened with the first gen Ryzen/Epyc and it was in an internal presentation. See
here. In terms of performance monolithic will always be the golden standard. MCM is merely a clever engineering trick for more cost-efficient production and extend the capabilities of what your current process node allows you. But the fact of the matter is that when you can produce efficiently dies with large number of cores (like Intel can do) going MCM to extend the core count versus going multi-socket is an interesting debate. Because there is only so much heat that you can dissipate from a single chip (regardless whether the chip is an MCM one) from a single socket. Having multiple sockets allows you to provide more power overall and clock the cores higher compared to when they are all in the same socket. Sure inter-socket latency is higher than inter-die latency but when you already have 18-28 cores in one monolithic die in one socket, virtually all-latency sensitive workloads are taken care off by that single cpu. Those workloads that need/scale to even more cores are most likely not latency-sensitive so going multi-socket doesn’t really affect them.
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