redgarl :
bit_user :
As with tensor cores, I think AMD was also caught off-guard by Nvidia's RT cores. If so, it will take them at least two generations before they have a chip early enough in the design pipeline to accommodate a response.
Nvidia is actually the one who will play catch up... because they have no Infinity Fabric. We've seen it during the presentation, Infinity Fabric second generation is now part of the GPU architecture.
They have NVLink/NVLink2. With Volta, it gives them 150 GB/sec of bandwidth (each direction) vs. 100 GB/sec that AMD has said 7 nm Vega can support.
That said, I prefer AMD's PCIe-based approach to Nvidia's proprietary solution. But let's try to be realistic.
redgarl :
Chiplet is the future and Intel/Nvidia are not even there at the start line.
Hmm... Intel has EMIB and whatever Cascade Lake AP uses. Both Intel and Nvidia have shipped solutions using HBM/HMC. I don't know what else you really need, in order to believe they can go this direction if they wanted.
redgarl :
Turing could have been done with Infinity Fabric, easier, cheaper and faster. Nvidia is about 3-4 years behind of their first chiplet design.
Are you fabricating this out of thin air? If not, then what's your source?
I disagree that Turing would be either faster or more energy-efficient as a multi-chip solution. The only upside of going that route would be cost.
redgarl :
Intel, at least 2 years before EMIB first implementation.
Really? I thought their Kaby Lake-G processors used EMIB.