I'm curious to know which process node the stacked SRAM dies are using. I'll bet probably TSMC N6, like the RDNA3's MCDs.
Given what's come out about poor SRAM scaling, I wonder if AMD is moving to an arrangement where they'll put far less L3 cache on their compute dies, and only their low-end CPUs won't have stacked SRAM.
Given what's come out about poor SRAM scaling, I wonder if AMD is moving to an arrangement where they'll put far less L3 cache on their compute dies, and only their low-end CPUs won't have stacked SRAM.