AMD Vega MegaThread! FAQ and Resources

[-Fran-]

Samsungs new Aquabolt, second gen HBM2, is pretty remarkable as well.

Samsung on Thursday announced it has started mass production of its second-generation 8GB High Bandwidth Memory-2 (HBM2). The package, dubbed Aquabolt, delivers data transfer speeds of 2.4 gigabits-per-second (Gbps) per pin which Samsung says translates into a performance boost of nearly 50 percent compared to its first-gen offering.

I played around in MS Paint and added Aqua Bolt for an easy comparison.

I think this makes the comparison easier to see significance of AquaBolt.

Edit: Aquabolt is one word!
2nd Edit: fixed picture!

Wait, how do you get 32GB capacity and a 3092-bit bus? That doesn't make sense.

You're correct. It doesn't add up.

"It comes in 8GB HBM2 stacks (8-Hi height) with speed of 2.4Gbps at 1.2V. It is is much faster than the previous generation (first-gen) HBM2 memory that offered maximum speeds of 1.6Gbps @ 1.2V and 2.0Gbps @ 1.35V."

"This second generation Aquavolt HBM2 memory with 1024-bit memory bus can deliver bandwidth of around 307GB/s per 8GB stack, which is huge"

http://graphicscardhub.com/gddr5-vs-gddr5x-vs-hbm-vs-hbm2/

You need to change the info in the table, goldstone

Cheers!

 

[AndrewJacksonZA]

Wow, Aquabolt is theoretically quick!!!

Here's to high production volumes for consumer cards!

 

[goldstone77]

I will fix it to 1024!
https://news.samsung.com/global/samsung-starts-producing-8-gigabyte-high-bandwidth-memory-2-with-highest-data-transmission-speed

* Editor’s Note:

[HBM2 and GDDR5 data bandwidth calculation]

-An 8GB HBM2 package’s data bandwidth: 2.4Gbps per pin x 1024bit bus = 307.2GBps

Using four HBM2 packages in a system: 307.2GBps x 4 = 1228.8GBps = approximately 1.2TBps

-A 8Gb GDDR5 die’s data bandwidth: 8Gbps per pin x 32bit bus = 32GBps

Added no. chips to 4

 

[-Fran-]

I will fix it to 1024!
https://news.samsung.com/global/samsung-starts-producing-8-gigabyte-high-bandwidth-memory-2-with-highest-data-transmission-speed

* Editor’s Note:

[HBM2 and GDDR5 data bandwidth calculation]

-An 8GB HBM2 package’s data bandwidth: 2.4Gbps per pin x 1024bit bus = 307.2GBps

Using four HBM2 packages in a system: 307.2GBps x 4 = 1228.8GBps = approximately 1.2TBps

-A 8Gb GDDR5 die’s data bandwidth: 8Gbps per pin x 32bit bus = 32GBps

Added no. chips to 4

The BUS would be 4Kbit, since each *stack* of 8GB is 1Kbit.

EDIT:
8GB = 1 stack = 1Kbit = 307.2GB/s
(...)
32GB = 4 stacks = 4kbit = ~1.2TB/s

Or at least, that is how I understand it.

Cheers!

 

[Sakkura]

The BUS would be 4Kbit, since each *stack* of 8GB is 1Kbit.

EDIT:
8GB = 1 stack = 1Kbit = 307.2GB/s
(...)
32GB = 4 stacks = 4kbit = ~1.2TB/s

Or at least, that is how I understand it.

Cheers!

That looks more like it, yes.

 

[goldstone77]

I fixed it to 4096-bit!

It's as impressive as I thought it was when I first read it.

 

[goldstone77]

BTW thanks to everyone for your help with the numbers! It's about time we are seeing some innovation with RAM! It has held back computing since inception!

 

[-Fran-]

Well, now the products seem to be being held back by supply and not innovation, haha.

Cheers!

 

[goldstone77]

You are full of wit today Yuka! But you are also right on target! The reallocated resources to produce other memory, so prices would spike. This year several fabs are supposed to come online, but we will not see any relief until ~4th quarter 2018-2019.

 

[-Fran-]

God darn it, AMD. God darn it...

https://techreport.com/news/33153/radeon-rx-vega-primitive-shaders-will-need-api-support

Cheers! =/

 

[goldstone77]

https://globenewswire.com/news-release/2018/01/23/1299430/0/en/Graphics-Industry-Leaders-Mike-Rayfield-and-David-Wang-Join-AMD.html

SharePrint
January 23, 2018 16:05 ET | Source: Advanced Micro Devices
SANTA CLARA, Calif., Jan. 23, 2018 (GLOBE NEWSWIRE) -- AMD (NASDAQ:AMD) today announced the appointment of Mike Rayfield as senior vice president and general manager of AMD Radeon Technologies Group (RTG), and David Wang as senior vice president of engineering for RTG. Both will report to President and CEO Dr. Lisa Su. Rayfield will be responsible for all aspects of strategy and business management for AMD’s graphics business including consumer graphics, professional graphics, and semi-custom products. Wang will be responsible for all aspects of graphics engineering, including the technical strategy, architecture, hardware, and software for AMD graphics products and technologies.

Anyone know anything about these guyz?

 

[-Fran-]

https://globenewswire.com/news-release/2018/01/23/1299430/0/en/Graphics-Industry-Leaders-Mike-Rayfield-and-David-Wang-Join-AMD.html

SharePrint
January 23, 2018 16:05 ET | Source: Advanced Micro Devices
SANTA CLARA, Calif., Jan. 23, 2018 (GLOBE NEWSWIRE) -- AMD (NASDAQ:AMD) today announced the appointment of Mike Rayfield as senior vice president and general manager of AMD Radeon Technologies Group (RTG), and David Wang as senior vice president of engineering for RTG. Both will report to President and CEO Dr. Lisa Su. Rayfield will be responsible for all aspects of strategy and business management for AMD’s graphics business including consumer graphics, professional graphics, and semi-custom products. Wang will be responsible for all aspects of graphics engineering, including the technical strategy, architecture, hardware, and software for AMD graphics products and technologies.

Anyone know anything about these guyz?

I don't know them, but my juvenile inner self is giggling at Mr. D. Wang's name. Let's hope he can erect the engineering division to glory and introduce great new products that penetrate new markets.

Cheers!

 

[goldstone77]

https://globenewswire.com/news-release/2018/01/23/1299430/0/en/Graphics-Industry-Leaders-Mike-Rayfield-and-David-Wang-Join-AMD.html

SharePrint
January 23, 2018 16:05 ET | Source: Advanced Micro Devices
SANTA CLARA, Calif., Jan. 23, 2018 (GLOBE NEWSWIRE) -- AMD (NASDAQ:AMD) today announced the appointment of Mike Rayfield as senior vice president and general manager of AMD Radeon Technologies Group (RTG), and David Wang as senior vice president of engineering for RTG. Both will report to President and CEO Dr. Lisa Su. Rayfield will be responsible for all aspects of strategy and business management for AMD’s graphics business including consumer graphics, professional graphics, and semi-custom products. Wang will be responsible for all aspects of graphics engineering, including the technical strategy, architecture, hardware, and software for AMD graphics products and technologies.

Anyone know anything about these guyz?

I don't know them, but my juvenile inner self is giggling at Mr. D. Wang's name. Let's hope he can erect the engineering division to glory and introduce great new products that penetrate new markets.

Cheers!

Hahaha, they had break out the Big D. Wang to combat Nvidia's well Huang CEO!
https://www.anandtech.com/show/12363/amd-reassembles-rtg-hires-new-leadership

He exudes confidence!

First off then, let’s talk about the engineering side. The new head of RTG’s engineering efforts (and arguably the de-facto successor to Raja) will be David Wang. Wang is a name that some long-time followers may be familiar with, as until earlier this decade he was a long-term AMD employee that rose through the ranks to become a Corporate Vice President of AMD’s GPU and SoC efforts. And as you might expect for someone hired for AMD’s top GPU engineering post, Wang has a long history in the graphics industry, working for SGI before joining ArtX and going through the ArtX-to-ATI-to-AMD acquisition chain. Specific to his experience at AMD, Wang has worked on every AMD GPU between the R300 and the Southern Islands (GCN 1.0) family, so he’s seen the full spectrum over at AMD.

More recently, he’s been serving as the Senior VP of Synaptics, where he was one of several former ATI/AMD employees to jump ship over there around the turn of the decade. So for David Wang, in a sense this is coming back home to AMD. Which off the top of my head makes him the third such high profile engineer to jump out and back in over the last decade, after Raja Koduri and CPU guru Jim Keller.

Wang re-joins AMD at a critical time for its engineering group. With the Vega launch behind it, RTG’s engineering staff is in the middle of development of the Navi GPU architecture and beyond, all the while putting the finishing touches on Vega Mobile for this year and squeezing in a 7nm Vega design for servers for 2019. Vega’s launch has been a contentious one – for engineering reasons as much or more so than business reasons – so Wang may very well be a much-needed breath of fresh air for RTG’s engineering teams.

Officially, AMD is stating that in his position, Wang will be responsible for “graphics engineering, including technical strategy, architecture, hardware and software for AMD graphics products,” the last item in particular being notable, as this confirms that software is staying under the control of the engineering group rather than being more distributed through AMD as it once was.

RTG Business Group Leadership: Mike Rayfield, Senior Vice President and General Manager

Continue by clicking on the link!

 

[goldstone77]

AMD Working On A Brand New Major GPU Architecture To Succeed GCN by 2020-2021
By Usman Pirzada
Feb 6

MD’s brand new macro architecture will have a similar (or greater) performance differential as the TeraScale to GCN jump
GCN was first introduced in 2011 to succeed the TeraScale series of micro-architectures and was one of the most disruptive innovations of its time putting the company firmly ahead of the competition (at the time) and putting immense pressure on NVIDIA. For the past year however, RTG has struggled to compete for the top spot in the graphics segment and all eyes are waiting for NAVI to arrive (probably in early 2019).

NAVI however, will be the last optimization and iteration of the GCN macro-architecture, the 6th generation to be specific. GCN has had a great run and marked a turning point in AMD’s philosophy when it moved from the VLIW (very long instruction word) to an RISC (reduced instruction set based computing) based approach. This meant that GCN required a vastly greater number of transistors on die then TeraScale (the predecessor to GCN) but also resulted in serious performance and GPGPU computational advantages.

It is known that this brand new architecture will result in a leap that is at-least as great as the TeraScale to GCN shift. Since the process will be the 7nm+ optimized node, we can be rest assured that yields will not be a problem (which makes sense considering AMD will want to focus only on the architecture and not bleeding edge node issues at that point). Since the company has other Zen 3 based optimizations planned for this time frame, it is now looking that the company is set to reaching its all-time high of market success on both CPU and GPU sides sometime in 2020/2021.

 

[goldstone77]

Cheats, Lies, and Video Games
AdoredTV
Published on Feb 7, 2018
https://www.youtube.com/watch?v=-0LSZJyA0F8&feature=youtu.be
[video="https://www.youtube.com/watch?v=-0LSZJyA0F8&feature=youtu.be"][/video]

Cheaters!

 

[Gon Freecss]

This is from a top guy at GloFo. So, it seems AMD will most likely be using TSMC in 2019. That process isn't as good, and Intel's 10nm process is even better than GloFo's (10nm+ is ~10% denser than 10nm and can hit higher clocks).

 

[goldstone77]

This is from a top guy at GloFo. So, it seems AMD will most likely be using TSMC in 2019. That process isn't as good, and Intel's 10nm process is even better than GloFo's (10nm+ is ~10% denser than 10nm and can hit higher clocks).

I read something about that this morning. I think Anantech mentions a interview with Lisa Su maybe where she said they were going to use TSMC 7nm. I think one reason was it will be ready before GlobalFoundries 7nm like that quote suggests. I'll look for it.

Edit: Also, if I remember correctly there was talk about this last year. And the payment from AMD to GlobalFoundries.

 

[goldstone77]

Getting Radeon Vega Everywhere: An Exclusive Media Interview at AMD Tech Day, with CEO Dr. Lisa Su
by Ian Cutress on January 24, 2018 8:00 AM EST
https://www.anandtech.com/show/12312/getting-radeon-vega-everywhere-an-exclusive-interview-with-dr-lisa-su-amd-ceo

Q18: With GlobalFoundries 14nm, it was a licensed Samsung process, and 12nm is an advancement of that. 7nm is more of a pure GF design. Is there any change in the relationship as a result?

LS: So in 7nm, we will use both TSMC and GlobalFoundries. We are working closely with both foundry partners, and will have different product lines for each. I am very confident that the process technology will be stable and capable for what we’re trying to do.

 

[Gon Freecss]

This is from a top guy at GloFo. So, it seems AMD will most likely be using TSMC in 2019. That process isn't as good, and Intel's 10nm process is even better than GloFo's (10nm+ is ~10% denser than 10nm and can hit higher clocks).

I read something about that this morning. I think Anantech mentions a interview with Lisa Su maybe where she said they were going to use TSMC 7nm. I think one reason was it will be ready before GlobalFoundries 7nm like that quote suggests. I'll look for it.

Edit: Also, if I remember correctly there was talk about this last year. And the payment from AMD to GlobalFoundries.

This will happen on the CPU front, which would be kind of a big deal.

 

[-Fran-]

I don't think AMD will use TSMC for their CPUs. APUs maybe, but not CPUs.

Cheers!

 

[Gon Freecss]

I don't think AMD will use TSMC for their CPUs. APUs maybe, but not CPUs.

Cheers!

GloFo might take too long. Last I heard, H2 2020 is when it will be ready.

 

[JamesSneed]

I don't think AMD will use TSMC for their CPUs. APUs maybe, but not CPUs.

Cheers!

GloFo might take too long. Last I heard, H2 2020 is when it will be ready.

At CES AMD said they would have 7nm Vega out end of 2018 albeit they were talking about machine learning so it may be low volume production at that point. Anyhow I'm pretty certain early 2019 we will see Vega 7nm and Zen 7nm. At least everything AMD is saying right now points that that timeline. There 7nm process can't come fast enough though as it should fix a large issue they have today, frequency scaling.

 

[Gon Freecss]

I don't think AMD will use TSMC for their CPUs. APUs maybe, but not CPUs.

Cheers!

GloFo might take too long. Last I heard, H2 2020 is when it will be ready.

At CES AMD said they would have 7nm Vega out end of 2018 albeit they were talking about machine learning so it may be low volume production at that point. Anyhow I'm pretty certain early 2019 we will see Vega 7nm and Zen 7nm. At least everything AMD is saying right now points that that timeline. There 7nm process can't come fast enough though as it should fix a large issue they have today, frequency scaling.

Yes, built on TSMC's 7nm process. GloFo is not ready yet, and probably won't be ready for 2019. Also, Zen 2 will debut in 2019, won't be just Zen shrunk down to 7nm. Even Lisa Su stated their products will first be released on "other 7nm" which means TSMC's inferior process.

 

[goldstone77]

I've made comments about this after Ryan Shrout's tour at the Malta Fab 8.
http://www.tomshardware.com/forum/id-3341285/amd-naples-server-cpu-info-rumours/page-28.html#20687647

TSMC taped out several 7nm chips last year and expects volume production this year. GF is a step behind with an in-house designed 7nm node taping out chips in late 2018 and mass production in 2019.

GF must prove to its customers, AMD among them, that its 7nm capabilities are competitive with TSMC. GF claims its 7nm LP process will provide for mobile processor applications as much as a 30 percent die cost reduction and a 40 percent better performance over its 14nm node.

AMD said (and GF confirmed) it will be splitting its 7nm production across both GF and TSMC. Which chips will be coming from TSMC versus GF is still unclear.

My understanding is AMD plans development of 7nm GPUs and CPUs at both foundries, selecting the best one for each option as late as possible. Given AMD has promised to ship 7nm Zen 2 CPUs and 7nm Vega and Navi GPUs by 2020, the window is closing on that selection process.

GF claims its 7nm LP process will provide for mobile processor applications as much as a 30 percent die cost reduction and a 40 percent better performance over its 14nm node.

This is kind of a hint, weather honest or dishonest in nature I do not know, that perhaps GloFlo will be making AMDs mobile CPUs.

AMD said (and GF confirmed) it will be splitting its 7nm production across both GF and TSMC. Which chips will be coming from TSMC versus GF is still unclear.

My understanding is AMD plans development of 7nm GPUs and CPUs at both foundries, selecting the best one for each option as late as possible. Given AMD has promised to ship 7nm Zen 2 CPUs and 7nm Vega and Navi GPUs by 2020, the window is closing on that selection process.

These statements are also hinting that there may be a process war between GloFlo and TSMC for both CPU and GPU business as per the wafer agreement waiting up until the last possible moment for GloFlo to produce results.

 

[renz496]

My most optimistic feeling when it comes to 7nm was we will see SoC type chip early 2019. Anything bigger probably won't be coming until mid 2019 at the earliest. Meaning 7nm Vega (meant for their machine learning stuff) won't be coming out until H2 2019. Also it depends how good TSMC and GF refining their 7nm process for bigger chip. Worse we could end up seeing 20nm repeat.