My main issue with the Chiplet strategy is that I was "hoping" that the B650 Single Chiplet was going to be equivalent to X570 in Connectivity.
Basically 1x B650 = 1x X570:
And X670 would just be double the connectivity options.
And hopefully they figure out how to stop wasting 1x SATA 6Gbps per PCIe lane.
1x PCIe Gen4 link should be worth 3x SATA 6Gbps ports with some bandwidth room to spare.
Or find a way to have the SATA co-exist with the PCIe ports.
Or match Intel's Z690 in total PCIe lane connectivity options.
Z690 gives you 16x PCIe 4.0 lanes & 12x PCIe 3.0 lanes.
If you convert the PCIe 3.0 lanes -> 4.0 lanes, you'll get 6x lanes worth of bandwith.
Let's say you lop off 2x of those PCIe 4.0 lanes and dedicate them to 8x SATA 6 Gbps ports
Then you could have 20x PCIe 4.0 lanes that are flexibly assigned & 8x SATA 6 Gbps ports for 4x PCIe Gen 4.0 or 2x PCIe Gen 5.0 connection to the cIOD.
Then double that with X670 and you'd have the ultimate connectivity machine =D