News AMD's Upcoming Phoenix CPUs to Feature Hybrid Design: Document

[Admin]

AMD's processor programming sC6VBknT2SYdbkLBvAAhm3e points to hybrid nature of AMD's Phoenix processors.

AMD's Upcoming Phoenix CPUs to Feature Hybrid Design: Document : Read more

 

[1_rick]

"Performance Cores marked at 01h and Efficiency Cores descripted as 1h"

Wat.

 

[ezst036]

Both of the major x86 CPU companies embracing big.little will likely forestall an ARM/RISC-V future for a while.

 

[AgentBirdnest]

"Performance Cores marked at 01h and Efficiency Cores descripted as 1h"

Wat.

Also, the very next sentence:
"we are dealing with AMD's codenamed Phoenix processor featuring Zen 4 and Zen 4 cores, but keep in mind that AMD calls them otherwise. "

Umm...

 

[1_rick]

Umm...

LOL!

Well, the screenshot below shows the numbers are 0h and 1h, so that's just a typo. And the sentence you quoted should've said "Zen and Zen C", and, funnily enough, that's how I read it. I had to go back to check to see that it was wrong.

Edit: actually, the previous paragraph correctly says "these are probably Zen 4 and Zen 4 c", so the entire sentence in the second paragraph is redundant, but that's the state of journalism today, now that all the copy editors have been fired.

 

[bit_user]

Both of the major x86 CPU companies embracing big.little will likely forestall an ARM/RISC-V future for a while.

Yeah, I think the author is wrong in saying this was about competing with Alder Lake. Phoenix is a N4 port of Zen 4 and should have no problem out-performing current Intel in laptops of comparable wattage, even with all big Zen 4 cores.

IMO, this is about two things (and I'm not sure which is the bigger concern for them):

1. Meteor Lake, scheduled to launch by the end of the year on the new Intel 4 node.
2. ARM-based laptops, powered by Qualcomm and Mediatek.

Apple could factor in, as well. I'm pretty sure it's a tertiary concern, since I think there aren't a lot of people switching to Apple at any given time, but it's got to be an ongoing concern for everyone in the PC ecosystem.

 

[ezst036]

Apple could factor in, as well. I'm pretty sure it's a tertiary concern, since I think there aren't a lot of people switching to Apple at any given time, but it's got to be an ongoing concern for everyone in the PC ecosystem.

Apple is coming up a lot more than people realize, as is Linux. https://gs.statcounter.com/os-market-share/desktop/worldwide

Microsoft doesn't command the 95% marketshare that they used to some time ago. Give it another year or two and Windows may not even be above 70%. When Windows does go below 70%, it makes me contemplate how that will force the market as a whole to shift.

 

[bit_user]

Apple is coming up a lot more than people realize, as is Linux. https://gs.statcounter.com/os-market-share/desktop/worldwide

Microsoft doesn't command the 95% marketshare that they used to some time ago. Give it another year or two and Windows may not even be above 70%. When Windows does go below 70%, it makes me contemplate how that will force the market as a whole to shift.

Cool chart. Doesn't say what's their data source, however. So, I take it with a grain of salt. For one thing, it's awfully suspicious the way Unknown fluctuates by almost a factor of 2, over a period of just a few months.

Note that ChromeOS and Unknown are also continuing to gain adoption - it's not only MacOS.

As this represents "Worldwide" usage, a lot of the fleeing from Windows will be in certain notable countries pushing to develop their own alternatives. They're certainly not going to jump on the MacOS bandwagon.

BTW, I assume ReactOS is classified as "Unknown". I used to be interested in it, but considering where most of the development seems to be happening, I think I'll stick to WINE on Linux, if I need to run any Windows programs.

 

[salgado18]

Cool chart. Doesn't say what's their data source, however. So, I take it with a grain of salt. For one thing, it's awfully suspicious the way Unknown fluctuates by almost a factor of 2, over a period of just a few months.

Note that ChromeOS and Unknown are also continuing to gain adoption - it's not only MacOS.

As this represents "Worldwide" usage, a lot of the fleeing from Windows will be in certain notable countries pushing to develop their own alternatives. They're certainly not going to jump on the MacOS bandwagon.

BTW, I assume ReactOS is classified as "Unknown". I used to be interested in it, but considering where most of the development seems to be happening, I think I'll stick to WINE on Linux, if I need to run any Windows programs.

Actually, if you view the entire historic data since 2009, Windows is in a constant decline, and the biggest factor for that seems to be OS X. Linux and Chrome OS did grow a little too, but by a very small amount.

 

[Kamen Rider Blade]

LOL!

Well, the screenshot below shows the numbers are 0h and 1h, so that's just a typo. And the sentence you quoted should've said "Zen and Zen C", and, funnily enough, that's how I read it. I had to go back to check to see that it was wrong.

Edit: actually, the previous paragraph correctly says "these are probably Zen 4 and Zen 4 c", so the entire sentence in the second paragraph is redundant, but that's the state of journalism today, now that all the copy editors have been fired.

Zen #C cores are just LapTop cores moved onto DeskTop/Server for usage with tunning for efficiency given the higher power/thermal budgets that the new platform allows.

The P-Core & E-Core label that started with ARM's big.LITTLE is just being re-used for ease of understanding by both Intel & AMD.

P-Core = Regular die area size Zen # core optimized for Maximum Performance.
E-Core = LapTop die area size Zen #C cores optimized for Energy Efficiency and Low Power.

 

[ottonis]

It's a good thing that AMD is embracing the big.LITTLE architecture with their upcoming generation of desktop CPUs.
In order for this concept to be effective, AMD will need some sort of analogon to the Intel thread director that will distribute computing load across different cores in the most sensible way. This includes a close collaboration with Microsoft and Linux in order to optimize their thread directors at the OS level.

 

[thisisaname]

Time will tell but rumours and speculation will not.

 

[-Fran-]

From what I've read elsewhere, Zen4c cores are just lacking cache and a bit of width in its execution pipeline, but it'll keep all the instruction set of Zen4. If so and true, then Intel should feel a tad embarrassed if AMD can support AVX512 on laptop and they can't even do that on desktop.

Regards.

 

[bit_user]

Intel should feel a tad embarrassed if AMD can support AVX512 on laptop and they can't even do that on desktop.

You know Intel used their Intel 7 process node for Alder Lake, right? While AMD is using TSMC N5 or N4, here. Based on what I've found, Intel's node has a density of 100 MTr/mm^2, while TSMC N5 has a density of between 138 and 173 MTr/mm^2. So, the first issue is that you're judging what Intel did on a less dense node vs. what AMD did on a denser one.

Second, we know that Golden Cove cores are huge and power-hungry. That translates into low perf/W and low perf/mm^2. To push the mean of these quantities into the competitive territory, Intel then had to find a way to balance them out with cores that offered as much perf/W and perf/mm^2 as possible. So, that argues for designing not just a smaller, more efficient core, but one that's as small and efficient as possible, while still offering as good or better per-thread performance than a thread on a P-core that's at full-occupancy. I think this last point is crucial for making them easier to schedule.

As a result, they achieved E-cores that deliver 54% to 60% of the performance, in 25% of the area and 20% of the power. That's quite an achievement, IMO. I don't know how shoehorning AVX-512 in there would've changed the balance, but I think it's a decision they didn't take lightly. They had lots of incentive to keep it, although the lack of it doesn't seem to be hurting them for most consumer apps.

 

[bit_user]

In order for this concept to be effective, AMD will need some sort of analogon to the Intel thread director that will distribute computing load across different cores in the most sensible way. This includes a close collaboration with Microsoft and Linux in order to optimize their thread directors at the OS level.

I don't want to get too far down a speculative rat hole, but I'd just point out that the more similar the cores, the easier the scheduling problem should be. If the main difference between them tuns out to be the amount of L3 cache, then it simply turns into a version of the same problem they have scheduling between cores with & without 3D V-cache.

 

[TerryLaze]

It's a good thing that AMD is embracing the big.LITTLE architecture with their upcoming generation of desktop CPUs.
In order for this concept to be effective, AMD will need some sort of analogon to the Intel thread director that will distribute computing load across different cores in the most sensible way. This includes a close collaboration with Microsoft and Linux in order to optimize their thread directors at the OS level.

Why would they need a different thread director?!
All they need to do is to make the cores properly announce to the OS that they are main or secondary cores and the thread director will work as well as it does for intel.
Maybe they need something additional for avx apps to use all cores.

 

[bit_user]

Why would they need a different thread director?!
All they need to do is to make the cores properly announce to the OS that they are main or secondary cores and the thread director will work as well as it does for intel.

The Thread Director(TM) is a hardware block in Intel's hybrid Gen 12+ CPUs.

Intel Architecture Day 2021: Alder Lake, Golden Cove, and Gracemont Detailed

www.anandtech.com

It simply provides information that the OS kernel can use to make thread-scheduling decisions. Whatever the OS does, to take advantage of the information it provides, is a separate thing.

For its part, I believe AMD must rely on performance counters. So, this relies more heavily upon the kernel to read and interpret those values.

 

[TerryLaze]

The Thread Director(TM) is a hardware block in Intel's hybrid Gen 12+ CPUs.

So it's the cores properly announcing their capabilities...

AMD has put a crapton of AI modules in the first ryzen, I can only assume those are still there, and I can further assume that AMD can make a new one for their hybrids.

 

[bit_user]

AMD has put a crapton of AI modules in the first ryzen, I can only assume those are still there,

Huh? When Ryzen 1000-series first launched, they mentioned something about a neural network-based branch predictor. No further detail was provided, but anything making predictions at the rate of the CPU clock is going to be a very simple and highly-specialized piece of logic. I have no idea if they even kept it around in later generations, but I don't recall seeing further mentions of anything like that.

Was anything else mentioned?

I can further assume that AMD can make a new one for their hybrids.

All I know is that they haven't announced anything like Intel's Thread Director (TM). That's not to say they won't, but I think we'll know if they add something equivalent, as it needs to be software-visible.

 

[-Fran-]

You know Intel used their Intel 7 process node for Alder Lake, right? While AMD is using TSMC N5 or N4, here. Based on what I've found, Intel's node has a density of 100 MTr/mm^2, while TSMC N5 has a density of between 138 and 173 MTr/mm^2. So, the first issue is that you're judging what Intel did on a less dense node vs. what AMD did on a denser one.

Second, we know that Golden Cove cores are huge and power-hungry. That translates into low perf/W and low perf/mm^2. To push the mean of these quantities into the competitive territory, Intel then had to find a way to balance them out with cores that offered as much perf/W and perf/mm^2 as possible. So, that argues for designing not just a smaller, more efficient core, but one that's as small and efficient as possible, while still offering as good or better per-thread performance than a thread on a P-core that's at full-occupancy. I think this last point is crucial for making them easier to schedule.

As a result, they achieved E-cores that deliver 54% to 60% of the performance, in 25% of the area and 20% of the power. That's quite an achievement, IMO. I don't know how shoehorning AVX-512 in there would've changed the balance, but I think it's a decision they didn't take lightly. They had lots of incentive to keep it, although the lack of it doesn't seem to be hurting them for most consumer apps.

What does manufacturing nodes and E-cores "prowess" have to do with what I said?

Intel doesn't support AVX512 on ADL or RPL because they didn't give the E-Cores support for it and couldn't make the asymmetric ISA work for the P-cores running AVX512.

If AMD can make the dense cores use AVX512, it'll mean their "bigLITTLE" implementation has symmetric ISA support on both types of cores. This is also assuming the Zen4 cores in the mobile versions do in fact support AVX512, which I haven't read anywhere being confirmed.

Regards.

 

[bit_user]

What does manufacturing nodes and E-cores "prowess" have to do with what I said?

I don't know how to explain it other than how I did. Short of telling you to go back and re-read my post, all I can say is that you're comparing apples and oranges.

If AMD can make the dense cores use AVX512, it'll mean their "bigLITTLE" implementation has symmetric ISA support on both types of cores.

Beyond what I said above, I would also suggest that AMD does not seem as keen on achieving the same degree of area & power-efficiency improvements between their big & little cores as Intel was. Read into that what you will, but I'm sure that also prominently plays into their differing approaches.

 

[Elusive Ruse]

Yeah, I think the author is wrong in saying this was about competing with Alder Lake. Phoenix is a N4 port of Zen 4 and should have no problem out-performing current Intel in laptops of comparable wattage, even with all big Zen 4 cores.

IMO, this is about two things (and I'm not sure which is the bigger concern for them):

1. Meteor Lake, scheduled to launch by the end of the year on the new Intel 4 node.
2. ARM-based laptops, powered by Qualcomm and Mediatek.

Apple could factor in, as well. I'm pretty sure it's a tertiary concern, since I think there aren't a lot of people switching to Apple at any given time, but it's got to be an ongoing concern for everyone in the PC ecosystem.

I came here to point that silly bit out haha, AMD is mopping the floor with Intel on the laptop side right now. The Zen 4 laptop CPUs have great performance at lower watts.

 

[TerryLaze]

Huh? When Ryzen 1000-series first launched, they mentioned something about a neural network-based branch predictor. No further detail was provided, but anything making predictions at the rate of the CPU clock is going to be a very simple and highly-specialized piece of logic. I have no idea if they even kept it around in later generations, but I don't recall seeing further mentions of anything like that.

Was anything else mentioned?


All I know is that they haven't announced anything like Intel's Thread Director (TM). That's not to say they won't, but I think we'll know if they add something equivalent, as it needs to be software-visible.

Ok I have no idea if these are individual modules all under one name or if they are the same module doing different stuff, in either case it's a crapton of different things.
At some point they also added storeMI.
https://www.amd.com/en/press-releases/amd-takes-computing-2016dec13

AMD SenseMI technology is a key enabler of AMD's landmark increase of greater than 40 percent in instructions per clock1, and is comprised of five components:

• Pure Power – more than 100 embedded sensors with accuracy to the millivolt, milliwatt, and single degree level of temperature enable optimal voltage, clock frequency, and operating mode with minimal energy consumption;
• Precision Boost – smart logic that monitors integrated sensors and optimizes clock speeds, in increments as small as 25MHz, at up to a thousand times a second;
• Extended Frequency Range (XFR) – when the system senses added cooling capability, XFR raises the Precision Boost frequency to enhance performance;
• Neural Net Prediction – an artificial intelligence neural network that learns to predict what future pathway an application will take based on past runs;
• Smart Prefetch – sophisticated learning algorithms that track software behavior to anticipate the needs of an application and prepare the data in advance.

 

[TerryLaze]

If AMD can make the dense cores use AVX512, it'll mean their "bigLITTLE" implementation has symmetric ISA support on both types of cores. This is also assuming the Zen4 cores in the mobile versions do in fact support AVX512, which I haven't read anywhere being confirmed.

Regards.

It will also mean that the small cores won't really be that much smaller or use that much less power...

 

[-Fran-]

I don't know how to explain it other than how I did. Short of telling you to go back and re-read my post, all I can say is that you're comparing apples and oranges.


Beyond what I said above, I would also suggest that AMD does not seem as keen on achieving the same degree of area & power-efficiency improvements between their big & little cores as Intel was. Read into that what you will, but I'm sure that also prominently plays into their differing approaches.

It sounds like you're trying to say "poor Intel couldn't cram AVX512 on the E-cores because their process node couldn't do it", to which I say: "who cares? they just didn't and that's that". Be it a decision out of necessity or not, it's irrelevant to the fact they tried to go asymmetric and failed to do so and now AMD may be able to keep the symmetry on a thinner core. How thin it is vs what Intel has accomplished, I am not delving into that as it is irrelevant to my point.

I don't know who's actually mixing apples with oranges here, sorry.

And I'll leave it at that.

Regards.