walkthetalk
Distinguished
PIII Xeon
Introduced October 25, 1999
Number of transistors: 9.5 million at 0.25 ?m or 28 million at 0.18 ?m
L2 cache is 256 KB, 1 MB, or 2 MB Advanced Transfer Cache (Integrated)
Processor Package Style is Single Edge Contact Cartridge (S.E.C.C.2) or SC330
System Bus clock rate 133 MHz (256 KB L2 cache) or 100 MHz (1–2 MB L2 cache)
System Bus width 64 bits
Addressable memory 64 GB
Introduced October 25, 1999
Number of transistors: 9.5 million at 0.25 ?m or 28 million at 0.18 ?m
L2 cache is 256 KB, 1 MB, or 2 MB Advanced Transfer Cache (Integrated)
Processor Package Style is Single Edge Contact Cartridge (S.E.C.C.2) or SC330
System Bus clock rate 133 MHz (256 KB L2 cache) or 100 MHz (1–2 MB L2 cache)
System Bus width 64 bits
Addressable memory 64 GB