nottheking :
As for the actual specifics of the interface they're using... That sort of information has been frustratingly scarce; I couldn't really come across anything beyond the little bit that has been circulating about; all that I've seen is that it's SOME SORT of 4-wide, 16-bit (which would be distinctly NOT serial) at the specified 1.6 GHz..
If you want to push the 50GB/s (x2) bandwidth through a 64bits wide (4x16) interface each way, that interface would need to operate at a minimum of 6.25Gbps per bit lane. With a 1.6GHz clock going in, that would likely round up to 6.4GT/s.
And PCI Express is considered a serial interface even in its x16 configuration - serial lanes operate independently, then the data passes through small FIFO buffers to align bytes across lanes and eliminate the need to delay-match PCB traces with the clock and implement de-skew circuitry on the chip as would be necessary on parallel interfaces.