Broadwell: Intel Core i7-5775C And i5-5675C Review

Page 8 - Seeking answers? Join the Tom's Hardware community: where nearly two million members share solutions and discuss the latest tech.
Toggle sidebar Toggle sidebar
Status
Not open for further replies.

It is a desktop CPU review. For most intents and purposes, desktop CPUs never get used in conjunction with laptop displays. I would say this is reason enough to strike laptop displays from resolution statistics when considering resolutions for desktop reviews.

As for dirt-cheap displays, they do not get much cheaper than $90 short of buying used, refurbished or from questionable sources and you can get unopened-new-in-box 1080p displays starting from about $100. If you have ~$100 to spend on a brand-new 1440x900 17-19" display, you can probably stretch another $10 for a 1080p 20-22" one.

Put another way: if you are so broke that you cannot spare $10 extra for a FHD display, you likely cannot afford an i5-5675C either.
 

You're forgetting that while eDRAM hasn't been shown that frequently in most PC devices... We've had a lot of cases of it having heavy use in consoles. Namely, the Xbox 360, Wii, (and also Wii U) all make critical use of eDRAM... And even "a few million units a month" is still quite high; even if we take the minimum defintion of "2," that still equates to 24 million units a year; putting you within an order of magnitude of those consoles: 83, 101, and 10 million respectively... And I don't think any of them hit 24 million units sold in a year! (granted, we may be overstating how many of the relevant CPUs Intel sells...)

And do remember, the first two were hampered by having to use 90nm silicon, which makes a big impact versus the 22nm Intel used for Haswell. (or the 14nm that may be in use for the Broadwell-generation ones) That puts Crystalwell's 22nm size of 85 mm² or so in rough line of what was seen for the 360 and Wii: about 70 mm² for the Xenos "daughter Die" and 94.5 mm² for "Vegas."

And in both cases, the chip was not one of the biggest cost sources of each machine; the main GPU core, and especially for the 360, the CPU; the DVD drive was also a major cost contributor. Yet in spite of all that, the Wii was known to be sold at a profit (of $200 for the hardware alone; $250 when bundled with a game) from day 1, and the 360 was sold at only a minor loss from its $300 launch price at first.

Given that both of those occured when there was likely little to no economy of scale in place, chances are that at worst, the pricing of those was comparable to Crystalwell, if not higher. (given that Intel's already shipped a few million of them)


I have my doubts that GDDR5 is the best comparison for the type of memory involved; as its main argument in favor as a comparison point is "it's more expensive." Certainly, I'd expect the pricing on some eDRAM module to be higher; that's why I didn't outright suggest it'd cost less than $1-2. However, GDDR5 is likely unsuited for such an application, given that it's got a much-higher latency than would be desired for its function as L4 cache. The biggest cost factor for eDRAM tends to be the extra space commanded by higher amounts of control circuitry, which makes DDR4 probably a better comparison, given its higher percentage of control space versus the actual space used by DRAM cells. Granted, there's no readily-readable open market for DDR4 to judge the actual price of the DRAMs, though it's likely not double DDR3, given that full DIMMs aren't even really going for double the price, and they're still solidly in the premium pricing phase.


Mostly, all of the above was already addressed by the likes of AMD and others when they built the Xenos and Hollywood GPUs, among other things. I'm not so certain that the costs of EDRAM per-cell are THAT much more over conventional DRAMs, and certainly WELL below the cost of SRAM. While not much has been said about the specific design of Crystalwell's eDRAM, I'd imagine it's not that much different from the "1T-SRAM" design patented by MoSys, and advertised heavily; it's also the type of eDRAM used for the Wii and Wii U.

In their design, it offers a few major advantages over SRAM: first off, each cell is about 1/3 as large, and secondly, the cell design (unlike 6T SRAM) does not require more than one layer of interconnects inside the cell itself, (that merely is necessary for just the bit/wordlines and control circuits) And lastly, the design can be used on just about any logic process without extra issue. (i.e, it costs no more per-mm² to fabricate than whatever other logic is on the same die, and is interfaced with as if it was SRAM)

I'm imagining that Intel, given that they are Intel, will likely be able to roughly match those advantages, and thus, per-cell, Crystalwell's eDRAM is costing them no more than 30-40% of what CPU cache SRAM would cost them... And likely a good deal less; what I've seen so far suggests Intel's logic fabrication costs only about 50% more (per mm²) than it does for DRAM on the same node and wafer size. In short, the extra cost of eDRAM over DRAM is likely less than 100%: merely that it overall size-per-cell-count is higher (due to added control circuitry) and that it's made using a more expensive logic process rather than a DRAM process.

While I'll admit that a lot of my information has largely just been "pieced together," what I've seen suggested the cost for Intel's full-scale 22nm logic is around 6-7 cents per mm², which multiplied by the 85mm² of (22nm) Crystalwell... Is about $5.10-$6.01. That price assumes the Crystalwell die uses the full scale and maximum number of interconnect layers that they use for, say, the main Haswell die. Integration costs would likely be significantly less than the cost of fabricating the die itself.


Well, I'd already posited that, even if a large price hike was needed, if they took the Pentium 3258 as a basis (currently retailing for $69 apiece) they could push up to an additional $50 onto it; at $119 they'd have a very attractive piece, that likely has a very healthy profit margin for Intel... Given I don't think they maintain the same 50% profit margin on their Pentium lines that they have on, say, their i5 and i7 lines.

Given the massive price hikes Intel has put in for existing new Iris Pro products, my estimate is that Intel is trying to feel out for the highest-possible profit margin they can ask for; i.e, they're pushing for a MUCH higher margin on their Iris Pro products. A definite confirmation is if we see, over the next few months, Intel gradually drop the price to bring them much closer to comparable non-Iris Pro CPUs.


That's a very good point, and all the more reason to recognize that there's purpose for benchmarks below 1920x1080; the rest of the world doesn't strictly follow the enthusiast's high-end preference.
 


Exactly, me still being one of them. People on this forum frequently seem to forget that they are the high-end enthusiasts when it comes to gaming. So let me just say this:

Everyone is not like you! I absolutely hate when people on here say no one uses 768p, because Steam even shows a solid 26% still do. 768p is still a standard in many televisions under 30" and in the vast majority of consumer laptops, too. But forbid I hath spoken of a television instead of a monitor and something non-enthusiast like a consumer laptop, I think I'll go away now.
 
Yeah .. no.

eDRAM is ridiculously expensive, especially the implementation Intel used. It's basically externally mounted SRAM, which we haven't seen since the days of the 486 and early Pentium, you know those little L2 cache sticks you plugged into the motherboard. They used to come in sizes ranging from 256KB to 2MB and were expensive as all hell. Eventually they just integrated the SRAM into the CPU die, at a smaller capacity running full speed.

When you manufacture memory there are two ways to do it, either static or dynamic. Dynamic memory (DRAM) requires a frequent clock refresh to keep the contents of it's memory and reading the cell requires it to be discharged and then recharged. This makes it slower but much cheaper then SRAM, you can get very large sizes out of a single chip and chain multiple chips together for a DIMM or other memory format. SRAM on the other hand stores it's contents inside cells that don't require constant refreshing and can read and write to any cell instantly. SRAM cells are an order of magnitude more complex to design (that's 10x btw). They require six transistors per cell vs DRAM's one transistor and one capacitor, this usually translates into a 6x better density while also requiring a different sort of control logic in addition to the regular DRAM one used by the MCU.

eDRAM is just SRAM placed on an external package with control logic that's slaved off a nearby CPU's memory bus. It's the modern equivalent to those L2/L3 cache sticks we saw with 486 and Socket 7 boards. It's ridiculously fast, 6~10x at a minimum and it scales much higher because it use's less power. That 100GB's is from a single package of 1024Mb SRAM memory, though I believe they are using stacking to get better densities.

In comparison to SRAM, both DDR3 and GDDR5 are very slow yet also very cheap. I can guaranty you that extra 128MB of eDRAM is costing them more then $80 per chip in actualized costs, probably around $100~$120 per CPU manufactured. Now if you scale up manufacturing of both the CPU and the required eDRAM chip along with amortizing the R&D costs, you can get to a cheaper price per unit. Remember this CPU requires a different production line, shadow masks, and assembly process, those are not cheap, in fact they are stupidly expensive.
 


Followed by 1600x900 and 1680x1050, if I recall correctly!

I made a post in another forum and GPUs and performance; we all like seeings numbers and looking/admiring at the best/fastest. But my GTX 670 and R9 280X are still great 1080p cards, and can handle 1440p gaming as well - heaven forbid I don't use Ultra settings. :-o These are fairly old cards, and they're still quite viable today, and will be tomorrow. Yet, somehow, the GTX 960, which is in the same class, sometimes gets called weak...

 

My point was that 768p is unlikely to be relevant to most people who can afford an i5-5675C.

Who, besides enthusiasts, high-end gamers and compute-dependent hobbyists or professionals spends over $250 on a CPU? How many of them still use a primary display with a native resolution lower than 1080p?

If you dig deeper in the Steam survey stats, you find that 25% of machines have 0-3GB RAM, which would make them 6-15 years old. I suspect the bulk of those lower resolution displays (that aren't tied to newer laptops) belong to those antiques and I doubt many owners of machines stretched so long and thin would be interested in dropping $280 on the new i5.


I'm still using an HD5770 to play at 1200p and I rarely need to go lower than medium details. In most cases, I prefer medium details anyway since it eliminates distracting eye-candy, many glitches and details I simply do not care about. I even tried a few games in 5760x1080 just for kicks and they were surprisingly playable with slightly lowered details but with three dissimilar displays, it did not take long to give me headaches.
 
By the benchmarks, it puts the on-board t about the ATI 250. That's NOT impressive. You can tell by the obvious out dates games to test on, the far lower resolution, and less details proves tom's trying to make it look better then it really is.
I dare you to compare to a REAL resolution, like 1920 x 1080 at FULL details on GTA 5 against a lower-end ATI 260x video card. (I bet the 260x would blow it away, must less any video card faster then that).
 


Yes but on average a R9 260x is $120 dollars on top of the CPU. You also cannot easily fit a 260x into a super micro case, most of which don't have a GPU slot.

They were not showing it being better than having dedicated but rather that it is decent for entry level and light gaming. And being as good as a low to mid level GPU is actually very good. Not too long ago anything onboard was only good for looking at papers, even flash would drag it to its knees.
 
are these numbers real?.............Not only does it match lower mid range cards, but it completely destorys AMD's APUs........
:shock:
Click to expand...

OMG a $270 APU is faster than a $130 one. Who would have thought.
Click to expand...

OMG why AMD not have a $370 APU to be faster then Intel $270 APU? WTF?
 

That's fundamentally incorrect. eDRAM is *NOT* SRAM, it's DRAM, in that it's made using a single transistor with a capacitor, rather than six transistors. The term "eSRAM" is used when SRAM is put on the same die as logic... Though in practice, the term's almost never used given that happens to be SRAM's primary use. (including on-die cache)

128MB of SRAM like that wouldn't even come close to fitting in the 77mm² size* that Crystalwell occupies, at least at 22nm. To get an idea of how much space Intel's SRAM takes up, take a look at the die for Haswell: the flagship (4 core+GT2 graphics) is well-known as 177mm². (roughly 21.8x8.1mm) By comparison, that makes each of the L3 cache blocks as 2.9x2.3mm... Or about 6.67mm²... For containing 2MB. Multiply that by 64, and you get 426.88mm², which is WAY higher than the 77mm² die size Crystalwell actually has, a clear sign the RAM cells do not contain anywhere near 6 transistors.

Further, very telling is that one of Intel's own slides about the die also reveals that at 93°C, the eDRAM only has a retention time of 100µs... Retention time, even at high temperature, is primarily a concern of DRAM, not SRAM, given, as you did note, an SRAM cell needs not refreshed; it's indefinite so long as power remains applied as it uses no capacitor. Beyond that, it DOES mention that the size of each RAM cell is 0.029µm²; getting an SRAM cell that small would require a fabrication process WELL more advanced than 22nm. Yes, information is a little scarce in that regard, (Press releases seem to be saved a lot more for advances in NAND) but what I've seen suggests that the typical size for a SRAM cell at 22nm would be 0.092µm²... Which is approximately three times the 0.029µm² figure Intel provided. As it happens, that's approximately the die area ratio between a DRAM and an SRAM cell.

The above makes it rather indisputable that Intel is using some form of traditional 1T DRAM cell arrangement for Crystalwell.

And do remember that this sort of arrangement has many years of success: as I mentioned in my prior posting, both the Xbox 360 and Wii make a heavy reliance on eDRAM on a secondary die to assist their GPUs, and in fact those die sizes were rather comparable, respectively at 70mm² and 94.5m². Together those two consoles have sold nearly 200 million units, and both have, on average, sold for a profit, so I feel that they demonstrate a strong precedent that what Intel is doing can be cost-effective and successful.

*Those paying attention will notice I suddenly went from describing Crystalwell's die size as being 85mm² to only 77mm². Prior statements were based on estimates; the latter is a correction after finding that Intel did actually give an official figure, just AFTER the chip's launch, and all the first wave of articles had already published.
 

The MoSys-style eDRAM is coined as 1T-SRAM and is marketed as an SRAM alternative. To achieve 1Gbit in less than a square centimeter, Intel likely had to use expensive trench capacitors and this means a significant chunk of what they saved on area compared to a regular SRAM chip, they spent in extra masks and wafer processing steps to etch those trenches and form the capacitors within.
 
... What I do like about this is the idea of a HTPC chip. Mine is getting a tad old and I think my HD5450 is going out because it acts funky.
Click to expand...

I've gone Z-Box 'crazy' the last few years, Jimmy.

With OS & SSD, you're in for $500-$600, easy. Sweet playback of video and snappy CPU performance -- plays older games just dandy. 15w or less.

Mobile Haswell/Broadwell or a Kabini/Temash APU ... maybe even an Atom. If Zoltac doesn't put the new Carrizo in a Z-Box, I'm going to drop them like a bag of dirt.

What we need is a fancy low-watt surround receiver.
 

Definitely correct; MoSys' trademarked "1T SRAM" is, at its core, really, just arranged in a way that it can substitute as a lower-die-area alternative to SRAM.

As far as the exact capacitor design Intel is using, I'll admit I can't seem to find any information suggesting whether they've gone for a stack capacitor or trench capacitor design. However, given that a look at the die shot shows that the vast majority is taken up by the memory array rather than logic, that leaves a few options open to the precise cell design; mostly, it's just constrained to some form of 1T, 1C DRAM cell.

Though I do recognize that the chip was manufactured using a significantly more expensive process than a typical DRAM cell; I'd estimate that, given the number of masking and interconnect layers, Crystalwell probably costs to make, per mm², comparable to an actual Haswell core. Granted, that's not a HUGE difference; as I'd mentioned above, what information I found suggested current prices (@22nm) of fabricating DRAM and similar devices works out to around 4 cents per mm², versus 6-7 cents per mm² for Intel's logic. (such as Haswell) Yes, that's just raw production costs, not scaled for yield and binning.
 


I was under the impression that it was just SRAM stuck on an external package due to it's insane bandwidth. Getting 100GB's from regular DRAM is extremely difficult without going into very wide implementations similiar to what GDDR has to do. So either way Intel is spending some premium money putting that stuff on that CPU. Future manufacturing techniques could make it cheaper though.
 

Using SRAM wouldn't have boosted the bandwidth by a whole lot; DRAM can achieve speeds of 1600 MHz, as Intel's sheet has shown, and going with SRAM would have, at best, let it match the rest of the logic clock rate, so about double; and in that case it really wouldn't help on the interface side of things.

eDRAM has a major advantage for bandwidth over separate DRAM solutions, including discrete packages like DIMMs, as well as even attached directly to a motherboard through BGA packaging; in both cases you eliminate any need for extra pins on the CPU/SoC package to connect to the RAM. (the extra 2 channels of memory controller are the main difference in pin count between LGA 1150 and LGA 2011, for instance)

As a result, the only connections can all be made within the CPU package, and given that the PCB they're mounted on doesn't use a particularly high surface area and will be sealed, it's far easier to handle simply putting a lot more layers (and traces per layer) upon it. As a result on-package eDRAM can connect with a substantially wider interface than you could get for off-package DRAM. Similarly, the tightly-constrained distances allow for the designer to push for that part to run vastly higher transfer rates than could be accomplished on separate devices.

A good example of that in practice might be the Xbox 360 again; even a decade ago it had little difficulty (in an era before DDR3 existed) of setting an interface of 32GB/sec between the main Xenos GPU die and its separate daughter die.

Overall, I'm increasingly optimistic that this sort of route may be the key to future improvements; a separate die is actually a cheaper option than a giant monolithic die, (as issues with binning mean costs actually kinda scale exponentially with size increases) and this sort of eDRAM can perform a "kill two birds with one stone" effect: CPU performance is largely constrained by memory latency (especially felt through Cache misses) and GPU performance is largely constrained by memory bandwidth. Both of these are addressed with a further cache layer like this.
 

AFAIK, the 1600MHz is just the clock frequency fed into the eDRAM chip and does not really mean anything - GDDR5 chips have been driven with 1500-1700MHz clocks for a while too and DDR4 will make it fairly common for desktop memory next year. The individual DRAM (sub-)array are still limited by the usual analog bit sensing magic but the much smaller arrays reduce sense line capacitance, allowing the RAS latency to drop from about 7ns for typical DRAM to 3.75ns for the CW eDRAM.

The interface is supposed to be some form of high-speed serial bus to reduce pad/trace count so I would expect it to run at 16Gbps or faster, otherwise the extra complexity would not make sense. Since this is a custom memory, there is no telling how much secret sauce Intel put in there. If all Intel wanted was a dumb DRAM with lower latency, they could have made the chip on a standard, inexpensive DRAM process and achieved most of the same results using less than half as much die space.

As I said in one of my earlier comments: it smells like a proof-of-concept for HMC. All the fundamental building blocks appear to be in there, apart from the die stacking.
 
I have and still do, work on skylake. It is VERY different to the previous cores, much tighter, with MUCH tighter lanes. You people will be shocked and surprised, as will AMD, bless them.
 


What do you mean by tighter cores and lanes???

 


Because the Intel solution would then be not only faster, but cheaper as well. AMD needs to work on getting their core performance up before even considering pricing their stuff out of the budget range.
 
This is exactly what I said to a buddy of mine about a month ago. Everyone is going on about how little Intel has done with CPUs over the past few years - presumably due to no real competition from AMD. Then people starting looking to Zen as being the real competitor for Intel and saying things like "Intel are in for a shock" - I had the view that Intel weren't resting on their laurels all this time - they've just been biding their time and doing amazing things in a hush hush manner. When Zen is released it will soon be completely obliterated by some of the tech that Intel would have been working on in the meantime - AMD has lagged too far behind for too long and love them or hate them, Intel is the benchmark when it comes to CPUs - period. They own this space, and these 2 chips have just rendered AMD APUs completely useless now. I'd be interested in this for a HTPC solution with some light gaming - League of Legends etc. This is impressive, however, like the article concluded, what a poor time for them to be released.
Click to expand...

intel probably had this chip designed in 2008 and has been sitting on it all this time waiting until amd tried to make a comeback only to have their faces shoved back down into the mud. " amd oh look what we did: ZEN!" intel: " <yawn> 2008 broadwell was sitting on a usb drive in a safe at intels secret underground vault, guess it's time to brush the dust off skylake soon as we get back from our hula dancing lessons in hiawaii, who wants to hit up the tiki bars?"

This brings us full circle. Intel’s Core i5-5675C and Core i7-5775C are the first socketed desktop processors with Intel’s most advanced on-die graphics engine, Iris Pro Graphics 6200.
Click to expand...
this is both a shot at AMD gpu's and Nvidia GPU's ^5 to intel 2 birds with one cpu throne... and i do mean throne, it's king over those gpus.

i wasn't impressed with haswell, nor am i impressed with broadwell, and sky lake seems like it's only going to be a minor incremental increase also. intel research and development team:
Engineer#1"same design on a smaller die and featuring support for directX12 lets call it something worthy of the place we smoked all that weed after we designed this in 2008..."
Engineer#2" you mean like while we were skiing in aspen?"
Engineer#1"nah i think we used that one already what about while we were big horn sheep hunting in montana?"
Engineer#@"hmmmm like big sky?"
Engineer#1"ya, or hey what about that lake we camped next to.....wait give me another hit off that blunt...ive got it! horn lake!"
Engineer#2" no dude, that's to politically incorrect, the boss might find out we were at a sex camp."
Engineer#1" oh right then he might put two and two together and figure out what we were really doing with all those sheee....ermR&D $$$$$$ as we pawned off that die shrink redesign on all those sheep."
Engineer#2" ya man, that was our best scam yet!"
Engineer#2" wait, what were you just saying about the sheep?
Engineer#1" uhhhhhh...... oh hey look we need another joint! let me get one out of the tent i'll be right back"
Engineer#2"oh, while you're in the tent would you mind throwing in another sdcard in the camera by the sheep corral, i think there some predator nearby, something keeps spooking every time i go to sleep, i'm trying to find out what it is."
 

True, the actual clock rate within the DRAM wouldn't be as quite as much of consequence; mostly I was saying that, given that was the only part where the RAM cell type would genuinely impact overall throughput, that there wouldn't be too much of a difference between using SRAM and DRAM for that application.

As for the actual specifics of the interface they're using... That sort of information has been frustratingly scarce; I couldn't really come across anything beyond the little bit that has been circulating about; all that I've seen is that it's SOME SORT of 4-wide, 16-bit (which would be distinctly NOT serial) at the specified 1.6 GHz..

The exact nature of the DRAM itself is still of a bit of interest... Though they couldn't have cut the space by OVER half: the 0.029µm² cell size is around the expected range for a DRAM cell @22nm, so Intel likely didn't do anything wild with the cell ITSELF; any extra space would be taken up in the organizational structure. As for how much space... Thankfully the slide told us that each "macro" had a total density of 17.5Mb/mm², which works out to a total of about 0.0545µm² averaged per cell, about 87.9% more space.

Space-wise, I'd suggest that the smaller array size (especially, the 256-length wordline) were probably the main contributor to the extra space the arrays took compared to normal DRAM... But also for good enough reason, as you pointed out yourself; such a short wordline is very likely the key component to how they got the RAS timing down so low. The other part I'd considered is that the threshold voltage may be a LOT less lenient than normal... As to be honest, the one figure that jumped at me the most was the abysmal 100µs retention time, or over a 99.8% reduction from the JEDEC minimum. Such an adjustment, while sacrificing retention, (thus requiring a refresh every few hundred thousand cycles instead of every hundred million or so) could increase sensitivity enough to make it even more responsive. Of course, by that point it starts to stray into the realm of "speculation."
 

if it helps:
according to intel:
the Intel® Processor Graphics Gen7.5-based Intel® Iris™ Pro 5200
products bundled a 128 megabyte EDRAM. The EDRAM operates in its own clock domain and
can be clocked up to 1.6 GHz. The EDRAM has separate buses for read and write, and each
are capable of 32 byte/EDRAM-cycle.
Click to expand...
1.6GHz is the max. clockrate. the aggregate width is 512-bit..?
 
Status
Not open for further replies.

TRENDING THREADS

Latest posts

Moderators online

Share this page

COMPANY
RESOURCES
FOLLOW
Top Bottom