Intel mobile architectures such as the Intel® Pentium® M processor include Enhanced Intel SpeedStep® Technology to optimize power and performance according to the demand on the system. The technology operates by providing multi-point operating modes (referred to as P-State, P0 being highest CPU frequency) on the CPU that increments or decrements the processor frequency depending on the demand. When there is negligible demand on the system and the CPU is idling,
it provides multiple processor sleep states (referred to as C-State; higher C-states such as C4 refers to deeper sleep state) that reduce the overall power consumption significantly.
http://www.intel.com/cd/ids/developer/asmo-na/eng/dc/centrino/286122.htm?page=3
Every interrupt will pull back the CPU from a deeper sleep state to C0 due to the interrupt handler that services the interrupts. This impacts the sleep state residencies that are critical to optimize the power consumed. There is also an energy cost associated in transitioning between multiple C-states.
If the interrupt rates are high, the power savings due to deeper sleep states are negatively impacted due to the decrease in sleep state residencies and the cost associated with C-state transitions. While Intel® platforms offer platform-specific C3-like states, they require long residency (multiple milliseconds) to fully amortize their transitional costs.
An aggressive interrupt rate can potentially negate the benefits of deep sleep states offered by the platform.