CPU Architecture: now the 1's and 0's we saw in previous post have to be arranged in sets. with each set meaning something so that several such sets of 1 and 0 can be feed into the cpu for an output.
these are instructions. every cpu arch has an instruction set which is used to direct a cpu to compute a result. It's like cpu vocabulary. The smaller is your vocabulary, the more effort it will take to communicate something. The larger it is the better is the communication and less is the chance of error.
As architecture improves, instruction handling improves. To understand instructions, consider this hypothetical example: Compute the result of 5x5. to execute this, you need to perform 5+5+5+5+5 right?
now suppose cpu architecture allows me three variables only as A,B and C. so I can store a value in A, then store another value in B then invoke the operator "+" and store the result in C.
to perform a simple task like 5+5+5+5+5, We have to use the above idea as below
A=5, B=5, A(5)+B(5)= C(10)
"clear" A
make C(10)=A, so A=10 now
Clear C, So C is empty again
now we have
A(10)+B(5)= C(15)
.
.
.
.
so on till
A(20)+ B(5)= C(25)
STOP
So we perform three steps of clearing A, performing C=A and then clearing C before each addition cycle.
we do this thrice to get to 25 so we actually end up performing 9 operations extra other than plain addition.
Now suppose a new cpu architecture allows you 6 variables
you just perform
A=B=C=D=E=5
A+B+C+D+E=F
STOP
while we used 13-14 steps using the first cpu's logic, our second cpu allowed us to write a shorter program which will be computed with less instructions as well since you are not clearing and reloading Values in register here.
so even though both CPU's have the same clock speed, and they both execute instructions at the same speed too, second cpu will be faster simply because it has less instructions to execute.
good luck
-satyam
copy pasted part of the above from an earlier thread:
http://www.tomshardware.com/forum/361905-28-core2quad-q9705-core-3450-faster