[SOLVED] Chipset and PCIe Lanes

[Christoph0]

Hello,

i have questions about datatransfer in general. Let's say i have two M.2 NVMe SSDs each connected via 4 PCIe 3.0 x4 to the chipset. The CPU is connected with 4 PCIe 3.0 x4 to the chipset. An GPU is directly connected with it's own PCIe 3.0 x16 lanes to the CPU.

Part 1
What happens when i stream data from my GPU to the SSD? The data must go through the CPU chipset connection, right? And when you copy data from one SSD to the other it shouldn't use the CPU chipset lanes?

Part 2
In general i want to know how the 4 chipset CPU PCIe lanes will become a bottleneck. I would like to know which path is used for different data (USB-Device, network connection, keyboard and the examples above), and a few more things.

It would be nice if someone could answer part 1. Something to read (links, books or nice keywords for google) for part 2 would also be nice.

 

[popatim]

1: Data doesn't thru the CPU but ti does manage the entire process. basically the Cpu says 'Take this block of data and put it there' over and over until it's done, using the ram as a middleman (buffer).

2: You'd need some very high bandwidth parts to bottleneck the DMI bus but lets say you have a GPU with 48GB ram, and a large very fast NVME SSD. Image loading 48GB of data into the GPU. Now the DMI bus is maxed out but only for about 15 seconds*, and now you try to move a file from one Sata SSD to another.

*This assumes a DMI/PCIe 3 bus.