Does anyone have any links to whitepaper discussion of this function as it relates to Conroe?
I don't know of any white paper discussions, but I can point you to my own feelings on HT and Conroe. I've actually brought this up a number of times.
http://forumz.tomshardware.com/hardware/modules.php?name=Forums&file=viewtopic&t=178335&highlight=
Basically, my feeling is that HT would work very well with the Core architecture because of it's wider 4-issue design and extra execution units. This should really help it sustain 2 threads. A major issue with Netburst and HT was that it divided up the system resources such as buffers and cache which had a impact on the performance of each thread. This especially became apparent while 1 thread stalled in Replay mode while still hogging resources. The Core architecture would avoid a lot of the resource issues because buffers and such are all already bigger as part of the 4 issue design. In fact the Reorder Buffer has actually more than doubled from Yonah even though the change was only from 3 issue to 4. Cache trashing between logical cores in Netburst would also not occur in Core because the shared L2 logic already exists and just needs to load balance for 4 logical cores instead of the 2.
My feelings is that if HT were to be introduced in Core the best time to do it would be when they transistion to 45nm. The increase in cache from 4MB to 6MB will ensure that each logical core has more resources while the shrink will provide room to alleviate the additional power and thermal loads. Even then, the concern that HT generates excessive heat is probably exaggerated. Heat in and of itself isn't bad, it's just when heat is generated without doing work which was the case when a thread was stuck in Replay in Netburst. Core doesn't have a Replay loop. Core's more power efficient architecture will also help.
Given the statements from Intel it's quite possible that there is some preliminary work with HT on Core. Initially they avoided saying whether HT was dead, and I believe they've always maintained that it was a great idea that has just been postponed until it's required. I would be disappointed if they didn't tinker around with different features that just haven't been implemented yet. HT was supposedly in Netburst since the first Pentium 4s even though it wasn't activated. The L1-L1 bridge in Core also appears to be a feature that was tried but hasn't been activated.
The question is whether it will be. Most likely not. Recently Intel has taken great lengths to differentiate Core 2 and Netburst so it wouldn't be wise to bring back Netburst until the memory has dulled a bit. Still it has shown benefits in server applications where multithreading is more common so if any product were to receive it it would be Xeons. Given that both Intel and AMD feel that the rush is to quad core, than a slower pace to 8 core and even slower beyond, HT would be a way for Intel to market higher threading without actually spending the extra transistors. That was the original plan for HT anyways.