Crash,
It isn't a QDR signal. It only uses a 4 bit prefetch with more I/O buffers. What they are doing is ramping up the memory bus speeds by a factor of 2.
If the system clock is running at 100MHz (For example) the memory I/O's would be clocked at 200MHz. That with the DDR signal and you get the DDRII400 speeds. What Anand said, "...the internal bus of the DDR2 modules we see now has been lowered to 100MHz for DDR2-400..." is right because he is talking about is the chips themselves.
Here is a quote from LostCirciuts...
<A HREF="http://www.lostcircuits.com/memory/ddrii/2.shtml" target="_new">"The only other thing that needs to be accomplished to manage the internal data flow increase is to double the clock on the I/O buffers so that they are running at twice the speed of the core. To sum this up, DDR II 400 will feature a 100 MHz (10 ns clock cycle; tCK) core and I/O buffers that are running at twice the frequency while outputting data using DDR mode. This results in output of four bits / clock which is equivalent to a quad pumped interface in terms of bandwidth."</A>
All they are doing is increasing the number if I/O buffers. That is where the magical speed comes from.
This is what I think Rambus is also trying to pass off as that Octal Data Rate. But if you look at all of the documentation, it is still a DDR signal but at 4 times the system clock verses the DDRII 2 times the system clock mumbo jumbo.
The only thing running at a true QDR datat rate is QDRSRAM.
See QDRSRAM.Com for more details on that stuff.
Got a LAN Party that you want people to know about?
Let me know about it.
