News DDR4-4000 Rumored To Be The New Sweet Spot For AMD Ryzen 5000 CPUs

[0112358]

...This article had no place on Tom's in the first place, this is Wccftech-grade random rumor, Tom's supposed to be better than that!

Disagree totally. Tom's is the first article on this news item -- that I've seen -- that is calling for a grain of salt. Moreover, others (not Tom's) throw out the 3800 MHz claim for Zen 2 as a fact...which it most definitely is not. I'm thankful for Tom's calling it like it is.

 

[InvalidError]

CAS Latency is how many clock Cycles it takes to deliver data from one of its column after the read command ... I assume that this follows circuit specific design , not like they have higher fail rate at production level ?

Like CPUs and GPUs, some DRAM dies are faster than others so they get binned based on how fast they are and you get a range of latency/frequency options all using the same dies depending on binning. Since DRAM needs to be perfect every time all of the time for a computer to run reliably, actual failures aren't an option unless you have ECC and even then, this is only intended a fail-safe mechanism to prevent data loss, not a normal operating condition so you still should replace the defective memory.

 

[hotaru.hino]

I know what Timings are , I was asking why are they made in different timings on the silicon level and sold for much higher price while they cost the same to make on the silicon level

It costs the same to make a 3090 as it does to make a 3080 since the 3080 is just a crippled 3090. So how come NVIDIA doesn't sell 3090s at the same price as the 3080?

Oh right.

 

[nofanneeded]

It costs the same to make a 3090 as it does to make a 3080 since the 3080 is just a crippled 3090. So how come NVIDIA doesn't sell 3090s at the same price as the 3080?

Oh right.

what crippled and what GPU ? this has nothing to do with CAS Latency

 

[InvalidError]

what crippled and what GPU ? this has nothing to do with CAS Latency

Yes it does: the difference between the 3090 and 3080 is binning. DRAM chips get binned too: some chips have faster row address decoders than others so they get different RAS latency, some have faster column muxes than other so they get different CAS latency, some have stronger sense amplifiers and write drivers so they get faster precharge/activation latency, some have better IO drivers/receivers than others so they can run at faster bus clocks, etc. Dies that simultaneously excel in multiple categories are the ones that end up costing 2X, 3X, 4X as much as budget-friendly 3200-16-18-18-28.

 

[hotaru.hino]

what crippled and what GPU ? this has nothing to do with CAS Latency

While you're correct in that manufacturing a chip, regardless of where it ultimately ends up, costs the same, you're incorrect in assuming that all of the manufactured chips can perform the same. At the sizes we're talking about per transistor, the tolerances shrink dramatically and so not every chip performs the same. So you have a choice: either you have one performance segment and toss the rest, which results in a lot of waste and an expensive product to the end user because you have to make up the cost somehow, or you can sell the chips that don't make the cut as a lesser performance tier, resulting in less waste and recouping more of the cost while potentially lowering the cost of the top end (but probably not, because it's the top end).

 

[nofanneeded]

Yes it does: the difference between the 3090 and 3080 is binning. DRAM chips get binned too: some chips have faster row address decoders than others so they get different RAS latency, some have faster column muxes than other so they get different CAS latency, some have stronger sense amplifiers and write drivers so they get faster precharge/activation latency, some have better IO drivers/receivers than others so they can run at faster bus clocks, etc. Dies that simultaneously excel in multiple categories are the ones that end up costing 2X, 3X, 4X as much as budget-friendly 3200-16-18-18-28.

Okay but how about specs ? when they manufacture a certain DRAM Chip , What are the numbers they aim at ? by design I mean ... like how many Cycles needed to fetch the read command ? This is much different that the max clock a CPU can reach ...

Lets say they Aim at CAS 15 , do they get better or lower by lottery? ?

 

[InvalidError]

What are the numbers they aim at ? by design I mean ...like how many Cycles needed to fetch the read command ?

While the external interface may have changed a couple of times, the fundamental structure of DRAM hasn't changed much in 30+ years beyond process-related tweaks. The DRAM cell array has been optimized to hell and back, DRAM manufacturers aim for whatever they can get on a given process for a given array size, with smaller arrays (lower capacity per die) being faster all else being equal.

Internally, DRAM does not care about cycles much beyond the external interface. The row address decoder is a combinational logic blob (no clock involved in its inner working) that takes some number of ns to do its job once a new address gets presented to it and the only use of the clock there is to know how many cycles to let the decoder do its thing before presenting the its one-hot output to the cell matrix, the column muxes are combinational logic blobs with a propagation time in ns too, same for the analog bits responsible for reading and writing DRAM rows. The cycles are just a more convenient way to work with it in an environment where everything else is on a clock. cycles = ( (worst-case delay for a given phase of the DRAM operation cycle in ns + safety margin) / clock period in ns) rounded up.

As long as you respect the DRAM's internal working speed by setting latency cycles to values proportional with the clock frequency rounded up, you should be able to raise the clock to whatever the DRAM's external interface can bear.

 

[cryoburner]

You're kidding right? A heavy premium? You do recall that 16GB of ANY kind of memory, including 2133mhz, was running that price a year ago right? And anything over 3000mhz was much closer to 200 dollars or more? 4000mhz DIMMs with CL15 timings, in a 16GB kit for 160 bucks seems pretty damn decent to me.

A year ago, 16GB of DDR4-2133 was about the same price as it is now. Even DDR4-3600 could be had for under $80 a year ago. Now two years ago, sure, something like DDR4-3600 would put you back upward of $140, and prices were more like what you describe closer to three years ago, but that was all due to a shortage that saw atypically-high pricing for a while.

In the current market though, $160 is a rather large premium for 16GB of RAM, at a time when it's possible to get DDR4-3600 for less than half as much. Keep in mind, we're talking about something that will typically only affect CPU performance by a few percent, making the performance gains more or less unnoticeable. One would probably be better off spending that money on a 32GB kit of DDR4-3600. Not only will it likely be more useful within a few years or so, but as was shown in Tom's Hardware's Ryzen memory testing article, running four-ranks of memory often provide as much or more performance as running two-ranks of higher-clocked memory...

https://www.tomshardware.com/reviews/amd-ryzen-3000-best-memory-timings,6310-2.html

And that's even assuming the 4000 kit would run at those speeds. Even the slide describes it as being like what DDR4-3800 is to the current processors, including the phrase "good luck!", which implies that not all 5000-series processors will manage those speeds.

 

[Darkbreeze]

Yeah, I guess it was more like a year and a half to two years ago. But it wasn't because of any kind of shortage. It was because of an ARTIFICIAL shortage and price fixing, which resulted in several DRAM manufacturers facing class action lawsuits.

So, as I'll correct myself, TWO years ago, RAM was about double the price it is now, across the board. It didn't much matter WHAT speed or quality, it was ALL expensive. Low latency stuff was exceptionally expensive. The current prices are comparatively very much acceptable with it still being so fresh in memory.

 

[Switch87]

I'm building a new PC with the new 5900X and a RTX 3080. The MB will be a MSI MEG X570 Unify.

For the memory was going to get the Patriot Viper Steel DDR4-3200 (2x 16GB) kit but with this news I'm unsure what to get. What do you guys recommend to future proof the pc as much as possible?

 

[InvalidError]

What do you guys recommend to future proof the pc as much as possible?

My main recommendation would be: not losing too much sleep over it.

Spending 2-3X as much on memory for 5-10% more performance makes very little sense in most cases unless you want to break overclocking or benchmark records.

 

[Darkbreeze]

Or have the extra money and don't mind spending it. I've seen a lot of people spend far more than the price difference between a CL14 and CL16 kit, or 16GB and 32GB kit, on over the top CPU coolers and fans that are probably a lot less necessary and offer less in the way of gains, when a significantly cheaper cooler would have still offered sub-80 degree peak cooling.

But, you are of course 100% correct that a lot of people do this with memory when it's completely unnecessary because nothing they run, or will run, exceeds more than 8-10GB of memory usage anyhow.

 

[Apollyon69]

What will happen if the Memory clocks are higher than the CPU clocks? no speed gain I suppose over the CPU clocks right?

Memories are pretty much trashing CPUs performance, for a long time now. For each instruction executed, the CPU have to wait many cycles until the sluggish (fastest) RAM writes the results, and that's also the reason for huges caches at several places (L1, 2, 3). Any RAM improvement will for certain help the processing path, there is a lot of room for improvements until it copes with CPU speed, like it was back in time, 15-20 years ago

 

[InvalidError]

Any RAM improvement will for certain help the processing path, there is a lot of room for improvements until it copes with CPU speed, like it was back in time, 15-20 years ago

More bandwidth may help but DRAM will never come anywhere close to catching up with CPUs' bandwidth and latency requirements. Despite how slow CPU progress has become, DRAM progress is still much slower. In terms of absolute CAS/RAS/etc. access times in ns, DRAM is only 1-2ns faster than it was 10 years ago so if a CPU did not have L1/2/3$, it would spend 90+% of its time with both thumbs up its butt waiting, even worse when you have multiple threads across multiple cores competing for access to memory rows.

 

[nofanneeded]

Memories are pretty much trashing CPUs performance, for a long time now. For each instruction executed, the CPU have to wait many cycles until the sluggish (fastest) RAM writes the results, and that's also the reason for huges caches at several places (L1, 2, 3). Any RAM improvement will for certain help the processing path, there is a lot of room for improvements until it copes with CPU speed, like it was back in time, 15-20 years ago

More bandwidth may help but DRAM will never come anywhere close to catching up with CPUs' bandwidth and latency requirements. Despite how slow CPU progress has become, DRAM progress is still much slower. In terms of absolute CAS/RAS/etc. access times in ns, DRAM is only 1-2ns faster than it was 10 years ago so if a CPU did not have L1/2/3$, it would spend 90+% of its time with both thumbs up its butt waiting, even worse when you have multiple threads across multiple cores competing for access to memory rows.

We have the RAM Technology but it is just expensive ... it is the same Cache RAM used in the CPU ...

 

[InvalidError]

We have the RAM Technology but it is just expensive ... it is the same Cache RAM used in the CPU ...

SRAM-based DIMMs still wouldn't solve the added overheads of data having to cross a memory controller interface and an external bus nor the bandwidth bottleneck of such an external bus especially if said bus has to accommodate signal integrity margins for going through both a CPU socket and any combination of one or two DIMM slots per channel.

SRAM isn't just expensive, it also has ~1/6th the density of DRAM, so you'd need to have 6X as many chips per DIMM to get the same capacity, which would be problematic for bus loading and ruin attainable bus frequencies, obliterating SRAM's speed advantage and introducing extra latency for buffer chips.

SRAM simply isn't practical as an external memory, doubly so if it has to be socketable.

 

[hotaru.hino]

We have the RAM Technology but it is just expensive ... it is the same Cache RAM used in the CPU ...

Even ignoring the costs that @InvalidError mentioned, the other problem is doing such makes the amount of main memory fixed. Imagine buying a processor with 16GB of RAM and that's it. Want to add more? Too bad. You don't need that much? Too bad.

 

[nofanneeded]

SRAM-based DIMMs still wouldn't solve the added overheads of data having to cross a memory controller interface and an external bus nor the bandwidth bottleneck of such an external bus especially if said bus has to accommodate signal integrity margins for going through both a CPU socket and any combination of one or two DIMM slots per channel.

SRAM isn't just expensive, it also has ~1/6th the density of DRAM, so you'd need to have 6X as many chips per DIMM to get the same capacity, which would be problematic for bus loading and ruin attainable bus frequencies, obliterating SRAM's speed advantage and introducing extra latency for buffer chips.

SRAM simply isn't practical as an external memory, doubly so if it has to be socketable.

Does not need to be dimm style , it can be made LGA style next to the CPU , I am Thinking like 1200 LGA memory modules with tons of direct paths to the CPU

 

[InvalidError]

Does not need to be dimm style , it can be made LGA style next to the CPU , I am Thinking like 1200 LGA memory modules with tons of direct paths to the CPU

If you made SRAM-based HBM-style die stacks, you would be limited to 1-2GB per 8-stack and that memory would need to be soldered to the CPU substrate since the thousands of extra pins on the CPU package that would be required to put the SRAM on the motherboard instead would be unmanageable, especially if you want enough sockets for a usable amount of system RAM and at that level of performance, 32GB would likely be the low watermark so you'd need to accommodate 32 stacks at a minimum.

 

[hotaru.hino]

Ultimately though there's even the question if unifying main memory + cache is necessary anymore. A lot of applications we use every day have such low latency requirements that it barely matters.

Don't get me wrong, there are applications we use that would benefit from main memory's performance improving, but checking your mail doesn't require a terabyte a second and picoseconds of latency between the CPU and RAM.

 

[InvalidError]

Ultimately though there's even the question if unifying main memory + cache is necessary anymore.

That isn't even a question, DRAM fast enough to negate the need for caches is simply not feasible and neither is SRAM large enough to negate the need for DRAM or some other form of larger-scale working memory.

The closest we may get to eliminating DRAM is switching to NVDIMM once endurance becomes high enough to not be an issue and L3 caches become large enough to make system memory speed non-critical. Though at that point, we may also have something like 4-8GB of HBM DRAM or similar as L4$ to reduce wear on the NVDIMMs.

 

[hotaru.hino]

That isn't even a question, DRAM fast enough to negate the need for caches is simply not feasible and neither is SRAM large enough to negate the need for DRAM or some other form of larger-scale working memory.

The closest we may get to eliminating DRAM is switching to NVDIMM once endurance becomes high enough to not be an issue and L3 caches become large enough to make system memory speed non-critical. Though at that point, we may also have something like 4-8GB of HBM DRAM or similar as L4$ to reduce wear on the NVDIMMs.

The question isn't asking whether or not if it's feasible given the current technology (or future technology). The question is asking whether or not it's even worth pursuing anymore period.

i.e., given the applications we use on a day to day basis, would flattening the memory hierarchy even improve practical performance? My money is on "no."

 

[InvalidError]

The question isn't asking whether or not if it's feasible given the current technology (or future technology). The question is asking whether or not it's even worth pursuing anymore period.

Worrying about whether something is "worth pursuing" is futile when it is impossible to begin with.

 

[hannibal]

I know what Timings are , I was asking why are they made in different timings on the silicon level and sold for much higher price while they cost the same to make on the silicon level

Same reason why not all cpus Are sold with same clockspeeds! Some memory can run tighter settings, in another those same setting would cause errors and that memory set has to use different settings so that it will run stable.
because memory that is very good is rarer They Are sold at higher price, and memory that can not run at fast settings Are sold at low price, just because the silicon is not so good as the good ones. So the manufacturing cost is the same, but quality is not. There is variation even in the same batch of memory.