We are talking about chip/die manufacturing and semiconductor engineering. So PCB design is largely irrelevant.
Well strictly speaking AMD has no manufacturing division so they cannot possibly take TSMC's approach. They simply use TSMC's manufacturing facilities and are using the design tools available. Of course, the big manufacturing decision AMD has made with regards to yields was to use multiple dies/chiplets and not follow the monolithic path that Intel had taken.
That's the beauty of higher IPC and higher core number. You can use lower frequency and still achieve higher performance all while achieving lower power consumption. That of course applies to applications that are heavily threaded which is what server workloads usually are. It should be noted here that IPC is a per workload metric. Up to and including 3000 series AMD's IPC improvements were what I would call cheap. Make the core wider so you increase throughput per core in a similar manner a larger core count would achieve. That benefited workloads like tile-based rendering that would also scale with more cores but did little to help workloads that wouldn't. 5000 series is a different beast. That being said some of the architectural elements of Zen3 such as unified L3 cache should have been there since Zen 2 at least, not to say since original Zen. It's almost like AMD purposefully introduced a knowingly flawed design with the original Zen only to correct one flaw at a time and appear like making massive IPC improvements each time. That coupled with the fact that they already moved to bigger cache and AMD is slowly running out of some easy core design tricks. They have one more with DDR5 and then I am wondering how good they will be with IPC improvements. I hope they are.
I don’t think anyone doubts the semiconductor engineering advances made by TSMC and Samsung. What is controversial is the naming of the nodes and how nodes of different manufacturers can be compared with one another. And since Intel is compared, in the minds of the uninitiated at least, unfavorably by the current state of affairs and their position appears to be worse than it actually is, they react. And the fact of the matter is that Intel’s 10nm+/10nmSFF is comparable to TSMC’s 7nm/7nm+ so clearly nm naming is no longer a scientific or technical metric but a pure marketing one.
As for the future, Intel’s 7nm slots between TSMC’s 3nm and 5nm nodes. TSMC will be using GAA for their 2nm node, Samsung for their 3nm one and Intel for their 5nm. In any case at least until 2025 Intel will be trailing TSMC. AMD is likely to move to TSMC’s 5nm by the start of next year and stay there until at least late 2023/early 2024. Meanwhile Intel will be using 10nm until mid-2023 so again they will be a node behind for the next 2 years. In mid-2023 Intel will move to their 7nm, at least for mobile surpassing AMD like with Icelake Vs Ryzen 3000 (Zen+) mobile. But then AMD moves to TSMC’s 3nm though this time around Intel will also utilise TSMC and their 3nm for some logic tiles. It will be interesting to see how all these pan out for sure.
We are talking about chip/die manufacturing and semiconductor engineering. So PCB design is largely irrelevant.
Lol, do you actually realize that PCB's are not just consigned to the Motherboard. The Multilayered board that the processor die is placed on is an ultra thin layer PCB made in the same way but for a different package. The materials can differ slightly (as in the case of Intel with its Fusion generator design (joke!)). So not sure if you really understand the worlds of ASIC Design.. But oh well, Another one loves to try to school me on matters they have no real knowledge about... Hence I was referencing my points to factual matters of ASIC level design, talking on the levels of reality of problems of Lithographic process that Intel tried and largely failed at (in yield success).
Well strictly speaking AMD has no manufacturing division so they cannot possibly take TSMC's approach. They simply use TSMC's manufacturing facilities and are using the design tools available. Of course, the big manufacturing decision AMD has made with regards to yields was to use multiple dies/chiplets and not follow the monolithic path that Intel had taken.
AMD used to own Global foundries which followed the same ethos that TSMC use. AMD had to sell it because of the nefarious practices of Intel and the cash flow problems stemming from it. AMD form K6 onwards followed it s own direction and still kept up the Ingenuity, despite Intel getting the game manufacturers and Microsoft to be tardy with the use of 3D Now....
Your use of Monolithic path was very grand and also pointless, as even when AMD owned Global foundries, they came with this ethos against Intel. And Samsung has a even more monolithic approach when it comes to finding success doing the same thing, with the same Tri-gate Die approach with 5 and 3nm products... Meaning that Intel's metrics are directly relevant to Samsung and Samsung are Streets ahead... TSMC is moving over theirs to the tri gate on the 3nm and Intel will have to cry cry cry, and buy the patient from Samsung to catch up.
It is for this purpose that Intel wishes to change the subject on the dynamic naming system. They simply have no argument against Samsung for the size and soon to be true for TSMC which will use the layered tri-gate approach at the behest of Intel.
My point was; the size issue that Intel touts is because of 2 things
1. Intel have pressed their Transistors too close to each other to reduce die size, making the chips furnaces in the process.. They will not last long as server chips or Data processing agencies, hence they will lose business.
2. The Competitors are about to use their own tri-gate transistors meaning that Intel will lose on that argument too... It thus must change the name game now....
Arguably AMD changed the performance metric in the early 2000 to equivalent performance metrics, because back then, as is the case now, Intel was just whacking up Frequency for IPC performance.
That's the beauty of higher IPC and higher core number. You can use lower frequency and still achieve higher performance all while achieving lower power consumption. That of course applies to applications that are heavily threaded which is what server workloads usually are. It should be noted here that IPC is a per workload metric. Up to and including 3000 series AMD's IPC improvements were what I would call cheap. Make the core wider so you increase throughput per core in a similar manner a larger core count would achieve. That benefited workloads like tile-based rendering that would also scale with more cores but did little to help workloads that wouldn't. 5000 series is a different beast. That being said some of the architectural elements of Zen3 such as unified L3 cache should have been there since Zen 2 at least, not to say since original Zen. It's almost like AMD purposefully introduced a knowingly flawed design with the original Zen only to correct one flaw at a time and appear like making massive IPC improvements each time. That coupled with the fact that they already moved to bigger cache and AMD is slowly running out of some easy core design tricks. They have one more with DDR5 and then I am wondering how good they will be with IPC improvements. I hope they are
Possibly true, but where is the evidence of this, what leads you to this belief? Making claims like this otherwise are fantastical, but you could after all be right.
I don’t think anyone doubts the semiconductor engineering advances made by TSMC and Samsung. What is controversial is the naming of the nodes and how nodes of different manufacturers can be compared with one another. And since Intel is compared, in the minds of the uninitiated at least, unfavorably by the current state of affairs and their position appears to be worse than it actually is, they react. And the fact of the matter is that Intel’s 10nm+/10nmSFF is comparable to TSMC’s 7nm/7nm+ so clearly nm naming is no longer a scientific or technical metric but a pure marketing one.
Again, you are missing the point. Intel's 10nm as with its 14nm uses Tri-gate design, so 3 transistors in one gate space where as TSMC can go 2 on planar. This is the only reason Intel can make this claim, and once TSMC moves over to the new Tri-gate process (which is soon; 3 years), Intel knows its argument is gone.
Intel is struggling shrinking its process to 10nm on a hit and miss basis. It probably has a yield success of 50% and less, so its shrink to 7nm is also a dream, if it cannot master the 10nm. It tried to use Cobalt to resolve the wire connection problems, but this is difficult to achieve, and it made little noticeable change in yields.
In other words; Intel must either buy the tech from its competitors (or at least rights to patents), or fall further behind.
TSMC is investing billions over the next 3 years, they know that Intel is losing Profit margins (despite what is claimed), and they have the most advanced Lithography that is for contract... Samsung is the most advanced, but it is in house.
But then AMD moves to TSMC’s 3nm though this time around Intel will also utilise TSMC and their 3nm for some logic tiles. It will be interesting to see how all these pan out for sure.
Considering Intel pay more for R&D than any other fab company, this is sickening for them.
AMDs success has been on the back of far less and from 'the Brink', they are now the leader in CPUs. Intel may claim some speeds, but at the cost of their reputation.
But yes, the future can yield many different possibilities, and it will be interesting to be sure. Remember Atom size is reportedly 0.1nm in size... It will be interesting...