Certainly. I'll just do a brief explanation:
Back in the Pentium III days we didn't have Double Data Rate (DDR) or Quad Data Rate (QDR) busses, nor AMD's HyperTransport bus. So multipliers were easy: A PIII 800E ran at a multiplier of 8x, 8x100=800. A PIII 800EB ran at a multiplier of 6x, 6x133=800. So the "B" in those days designated the higher 133MHz bus speed. The CPU had 2 pins that were either connected or not, the board would read those two pins and determine which bus speed was appropriate.
AMD came out with a Double Data Rate bus called the 200MHz bus. It was actually 100MHz, where 100MHz represents the electrical frequency, but 200MHz represented the rate that data was cycled. DDR cycled data twice per clock cycle. DDR SDRAM is based on the same principle.
Intel followed with a Quad Data Rate bus, which cycled data at 4x the frequency of the bus. So now we get up to current Intel technology:
18x100=1800, the P4 1.8A had a bus speed of 100MHz, with a data rate of 400MHz, so it was called a "400MHz" bus.
18x133=2400, the P4 2.4B had a bus speed of 133MHz, with a data rate of 533MHz, so it was called a "533MHz" bus.
18x200=3600, the P4 3.6E has a bus speed of 200MHz, with a data rate of 800MHz, so it's called an "800MHz" bus.
Notice all three of those had the same 18x multiplier, and that the 18 was multiplied by the electrical frequency of the bus, not the data rate. All 3 had the multiplier "locked", it couldn't be changed. Changing the bus speed would therefor change the CPU speed.
Believe it or not there are a few boards that can support all 3 of those processors, and the way it knows the difference is still by detecting which of 2 pins are connected or disconnected.
Intel has very few 1066 bus processors (266MHz clock, Quad Data Rate). If you put an 800 bus processor on a 1066 bus capable board, it will choose 800 bus rather than 1066 bus.
Now if that sounds like marketing trickery, consider AMD's 2000HT bus...
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