No worries, mate ... hope I didn't come off as a *ick. We're all here to share and learn
(other than the trolling fanbots
!)
It's simply a test run of the manufacturing of the die. TSMC has XXX capacity of 28nm wafer-starts. When they roll, they want to roll wide-open and produce high-yield stuff.
There are certainly others around with better knowledge, and the ""*multi-project* test-spins -- wild mix of CPU and GPU dies"" is simply a crazy scientific-method guess - LOL
As an example, AMD has entered *tape-out* on the
Kaveri APU (Son of Trinity), or certainly will in the next month or so. Kaveri is 28nm Piledriver CPU modules and 28nm
Cape Verde GCN cores connected via a unified memory structure.
TSMC and AMD drag some over-lapping design/process forward with Kaveri while working in the new stuff, too, and 'building bridges' to the next-gen Steamroller.
It would also not surprise me to hear that Germany and Taiwan (along with Luther Forest) jet unfinished wafers between each other and share mask-sets. These are all smart design/process guys (and girls), and AMD, now fab-less, wants to sync-up across as much product as possible.