News Gigabyte's B550 Motherboard Is PCIe 4.0 Heaven

[cloroxman1]

Is the fourth m2 slot under one of the others or under a heatsink or something?

 

[COLGeek]

Is the fourth m2 slot under one of the others or under a heatsink or something?

There are only 3. Please re-read this passage from the article:

As spotted by BenchLife, the B550 Aorus Master seems to arrive with three PCIe 4.0 x4 M.2 ports. That's a pretty big deal since most B550 motherboards only bring PCIe 4.0 support on the primary PCIe x16 slot and M.2 slot. Therefore, the primary M.2 slot is likely linked to the Ryzen chip, while the other two M.2 slots share bandwidth with the PCIe x16 connection. There's a good possibility that the PCIe switches partition the PCIe x16 slot and secondary and tertiary M.2 slots to run at an x8, x4 and x4 configuration, respectively.

 

[cloroxman1]

Then what does it mean x4 M.2 ports ?

 

[COLGeek]

Then what does it mean x4 M.2 ports ?

It refers to the relative bandwidth of the port, much like how PCIe slots are labeled.

 

[cloroxman1]

PCIe

It refers to the relative bandwidth of the port, much like how PCIe slots are labeled.

Correct me if I'm wrong, but the relative bandwidth is not that. It is determined the PCI spec, as in PCI 4.0
So the way I see it as written three PCIe 4.0 x4 M.2 ports.

It says three PCIe ( that is a slot )
pcie slot1 4.0 speed
pcie slot2 4.0 speed
pcie slot3 4.0 speed

x4 m.2 ports - means 4 m.2 ports - m.2 is a socket, not bandwidth.

Should say three PCIe 4.0 x16 ( shared/split ) x3 PCIe 4.0 M.2 ports.

 

[COLGeek]

PCIe


Correct me if I'm wrong, but the relative bandwidth is not that. It is determined the PCI spec, as in PCI 4.0
So the way I see it as written three PCIe 4.0 x4 M.2 ports.

It says three PCIe ( that is a slot )
pcie slot1 4.0 speed
pcie slot2 4.0 speed
pcie slot3 4.0 speed

x4 m.2 ports - means 4 m.2 ports - m.2 is a socket, not bandwidth.

No, it means three of the x4 type of M.2 port. Not four slots/sockets/ports. You are simply misreading the statement.

See here as well: https://www.techpowerup.com/267176/...-limitations-to-provide-three-gen-4-m-2-slots

 

[cloroxman1]

No, it means three of the x4 type of M.2 port. Not four slots/sockets/ports. You are simply misreading the statement.

See here as well: https://www.techpowerup.com/267176/...-limitations-to-provide-three-gen-4-m-2-slots

I read it, not going to argue but the way it is written is not correct

Again, as written - three PCIe 4.0 x4 M.2 ports exactly reads as follows

3 PCIe 4.0 slots - ( doesn't state the sizes or bandwidths of those slots ), usually something like x16,x8/x0/x8,x8/x8,x8

x4 m.2 - means there are 4 m.2 ports of unknown speed

This should read
3 PCIe 4.0(x16,x8/x0/x8,x8/x8,x8 example ) x 3 PCIe 4.0 M.2

 

[COLGeek]

I read it, not going to argue but the way it is written is not correct

Again, as written - three PCIe 4.0 x4 M.2 ports exactly reads as follows

3 PCIe 4.0 slots - ( doesn't state the sizes or bandwidths of those slots ), usually something like x16,x8/x0/x8,x8/x8,x8

x4 m.2 - means there are 4 m.2 ports of unknown speed

This should read
3 PCIe 4.0(x16,x8/x0/x8,x8/x8,x8) x 3 PCIe 4.0 M.2

Sorry, but the x4 is in reference to the bandwidth/type of M.2 port, not the number of M.2 ports.

Maybe it could be clearer, but both the TH and Techpowerup articles make it clear that there are only a total of three M.2 ports.

Have a good day.

 

[logainofhades]

The x4 is in regards to how many PCI-E lanes the slot has. Like how a single graphics card slot is x16, or if you run dual graphics cards, both slots would run at x8, as the available 16 lanes, for graphics, are split in half. Same for the little x1 slots, that get used for network adapters, and such. Those have a single PCI-E lane.

 

[InvalidError]

I'd like to see a future I/O chip from AMD integrate flexible switching capabilities, but again if it is too good it would compete directly with their own HEDT platform.

Before AMD worries about mainstream competing with its HEDT, AMD needs to catch up with Intel: Intel's H-series chipsets have 30 IO total lanes between PCIe, SATA, USB and Ethernet vs 18 for AMD's B-series. AMD is way behind on total IO and flexibility.

 

[vov4ik_il]

Before AMD worries about mainstream competing with its HEDT, AMD needs to catch up with Intel: Intel's H-series chipsets have 30 IO total lanes between PCIe, SATA, USB and Ethernet vs 18 for AMD's B-series. AMD is way behind on total IO and flexibility.

While that is totally true, for now, there are not too many consumer systems that utilize all the IO available.

In addition, chasing the fastest interfaces available, we often forget that interface speeds are limitations to only those components that have the interface as their bottleneck which are very few high-end devices to start with, while by the time the technology becomes mainstream and devices affordable, the early components that accommodate new interfaces become obsolete.

Test yourself: how many of us have NVMe drives that read and write 5000MB/s? How old is the motherboard you use?

 

[InvalidError]

Test yourself: how many of us have NVMe drives that read and write 5000MB/s? How old is the motherboard you use?

Since you are responding to my post about chipsets, I'll take this in the context of chipset IO. If your chipset's uplink only does 4GB/s, then you can't hit 5GB/s regardless of how much faster your secondary NVMe SSD is, so you need faster uplink to make any use of that. You also need a faster uplink if you want to have some spare bandwidth for everything else that is going through the chipset.

I don't own any "very-high-end devices" but I do own a fair number of slower ones and I do like having enough IO on my motherboard to spare me the trouble of having to swap hardware on an as-needed basis.

 

[vov4ik_il]

I'll take this in the context of chipset IO. If your chipset's uplink only does 4GB/s, then you can't hit 5GB/s regardless of how much faster your secondary NVMe SSD is, so you need faster uplink to make any use of that. You also need a faster uplink if you want to have some spare bandwidth for everything else that is going through the chipset.

In my example, an interface that has been available for a while (NVMe) and is already widely used, is still not being fully utilized (not too many drives hit the interface limitation). This context applies to many other interfaces.
With regards to IO lines availability (quantity, not BW), a typical system does not use most of what is available.

Edit: Here are some tests of PCIe 3.0 16x vs 8x in a typical application (gaming). The tests are 4 years old but the idea is there. Most of the interface bandwidth is far from being utilized in a typical use case.
Edit2: Here is a more recent run. Not much has changed.

 

[InvalidError]

Edit: Here are some tests of PCIe 3.0 16x vs 8x in a typical application (gaming). The tests are 4 years old but the idea is there. Most of the interface bandwidth is far from being utilized in a typical use case.

If you are going to bring GPUs into the equation, 3.0x8 vs 4.0x8 allows the 4GB RX5500 to achieve nearly double the fps in scenarios where it starts to get VRAM-bound, bridging most of the difference between the 4GB and 8GB variants. 4.0x16 will make the difference between next-gen low-VRAM GPUs being unusable or being able to compete against similar cards with twice as much VRAM.

Low-end components can benefit from high bandwidth too. In some cases, more so than high-end parts. I personally like the idea of having 4.0x16 for the GPU and not have to worry about running out of VRAM until I go far enough overboard that PCIe bandwidth cannot keep up with the amount of system memory the GPU needs to use.

 

[escksu]

Don't be too happy...PCIE 4.0 is limited by CPU, not board/chipset.

Ryzen has just 16 PCIE 4.0 lanes. This excludes:

1. 4 meant for chipset downlink
2. another 4 dedicated for nvme.

IF the board has 3 x PCIE 4.0 nvme slots. That would need total of 12 lanes. Minus the 4 dedicated for nvme, you still need 8. So, those 8 lanes have to come from somewhere. So, I believe they will take from those 16 lanes meant for GPU. This means you will be left with 8 for GPU and dual GPU may not work (unless its split into 4/4).

Also, its likely shared with those PCIE slots. Can see from the photo that 2nd and 3rd slots are 4x only. So, its likely you cannot use them in conjunction with nvme slot.

 

[InvalidError]

Don't be too happy...PCIE 4.0 is limited by CPU, not board/chipset.

If this is in response to me, then you need to keep in mind that B550 boards showed off so far are halo products and may not reflect typical B550 setups. Based on the solid majority of B450 boards having only the single NVMe slot connected directly to the CPU, I'm expecting most B550 boards to only have one and the few that do get two to use 3.0x4 from the chipset at the expense of one 3.0x4 PCIe slot or SATA ports as is typical for B450 boards.

Spraying high-speed switches all over the board to enable post-manufacturing IO flexibility is not something motherboard manufacturers can afford on mainstream boards with razor-thin margins, so those get mostly if not entirely hard-wired IO to cut costs.

 

[escksu]

If this is in response to me, then you need to keep in mind that B550 boards showed off so far are halo products and may not reflect typical B550 setups. Based on the solid majority of B450 boards having only the single NVMe slot connected directly to the CPU, I'm expecting most B550 boards to only have one and the few that do get two to use 3.0x4 from the chipset at the expense of one 3.0x4 PCIe slot or SATA ports as is typical for B450 boards.

Spraying high-speed switches all over the board to enable post-manufacturing IO flexibility is not something motherboard manufacturers can afford on mainstream boards with razor-thin margins, so those get mostly if not entirely hard-wired IO to cut costs.

Hi, thanks for replying. Although my comment is not targeting at you. Its just a general one for those who think 3 x nvme slots will be awesome.

Because this is ryzen and not threadripper, so some corners needs to be cut.

I fully agreed with what you have said.

 

[InvalidError]

Because this is ryzen and not threadripper, so some corners needs to be cut.

I wouldn't call it "cutting corners" when boards that do nothing more than exposing CPU and chipset IO in a basic hard-wired manner already have more IOs than most people know what to do with. The gilded boards may feel more cost-cutted due to the much higher number of mutually exclusive IOs but that is only because the board manufacturers are trying to fill specific niches that the platform may not be intended for... or just because they can and want to let loose on at least one model.

 

[alextheblue]

Before AMD worries about mainstream competing with its HEDT, AMD needs to catch up with Intel: Intel's H-series chipsets have 30 IO total lanes between PCIe, SATA, USB and Ethernet vs 18 for AMD's B-series. AMD is way behind on total IO and flexibility.

AMD's got more available bandwidth, it just isn't as flexible (although for me, it's actually a better setup). So it isn't lanes that is the problem, its how they're dishing them out.

But really what I was trying to say was they probably won't get too aggressive for their consumer platform. For example if AM5 had a x16 4.0 uplink, and the chipset handled everything outside of 1-2 PCIe slots (well, and the memory interface), that might be enough to handle a lot of HEDT use cases for 16 cores or less. They don't want to rob too many sales from their HEDT platform.