Guys...
What this means is that out of the 10-20 layers of metal on the chip (they were around 9 or 11 a while back; I expect that number has gone up substantially now), the bottom few - which are the ones that are the smallest and closest together (because higher levels cannot be small-featured due to surface bumpiness caused by lower-layer structures) - need to be manufactured as two masks instead of 1. The one problem I see with this is that if you need to have a single metal structure with two close-together features in it, that would require a portion of the structure would be in one mask, and a different portion would be in the other mask, and I don't know if the process can allow for that without causing excessive surface variation at the point of intersection. Is that actually a problem? I can't envision a scenario in which it would be. So ultimately this means that the circuit design tools need to create two masks instead of one, for a given low-level metal layer. The design tools already create multiple layers per mask anyway (positives, negatives, intersections with vias, etc.), so not really a huge issue. Either Intel ran into this too (and notice you didn't hear about it...), or they employ a different technology to lay down and mask their metal layers. I suspect the former.
This does mean that existing masks cannot simply be scaled down, however. So an IC designer such as AMD cannot simply send the same mask binaries and request a smaller process size. Instead, they need to regenerate the mask binaries using the new process rules. Chances are, other differences in the new process would have necessitated this anyway, so again, no big deal.