At SC11 in Seattle, the first processor with hardware transactional memory (HTM) was presented under the official name PowerPC A2.
At the beginning of 2013, Intel will also offer HTM, with its Haswell processor. Everyone from Intel openly admitted as much when asked directly at SC11. Supposedly, Intel will soon announce the new TM instructions that will be added to the already released AVX2 extension. It's about time, as the continually increasing number of processor cores makes the need for technologies for faster thread synchronisation more and more urgent. Without such technologies, the processor will eventually be so busy with itself that it won't be able to get any real work done.
With transactional memory, the idea is to not lose time by locking successive data access by threads to shared memory areas, but instead first bundling the accesses into an atomic transaction, for instance in the L1 cache, in order to save time by executing them all at once during the commit. This happens under the optimistic assumption that no other thread will stick its oar in and access the shared memory in the meantime. If that happens, though, that's bad luck and a rollback mechanism is required to abort the intended – but by then invalid – transaction. In that case, the transaction is re-executed, if applicable with new source data.
Although first leaked benchmark results for the Llano successor Trinity with the new Piledriver core can't really impress with a performance increase of 23 to 35 per cent in graphics (3DMark Vantage) and 7 to 17 per cent in general (PCMark Vantage), but at least the graphics performance should be more than sufficient to keep the Ivy Bridge in check in this context.