[SOLVED] How are the PCIe lanes of AMD CPUs allotted to the slots and chipset?

[rvidd]

In Intel, the PCIe lanes from CPUs are directly connected to the x16 slots and maybe few x4 slots or NVMe slots. Additionally 4 lanes are given to the PCH via DMI 2.0/3.0.

Does AMD allot the PCIe lanes same as Intel or they do it differently?

 

[rocktalkrock]

This diagram shows the PCIe lanes for the X570 chipset.

https://cdn.wccftech.com/wp-content...X570-Chipset-Details-and-Specs_1-1480x832.png

 

[rvidd]

This diagram shows the PCIe lanes for the X570 chipset.

https://cdn.wccftech.com/wp-content...X570-Chipset-Details-and-Specs_1-1480x832.png

In that architecture diagram, what is "4x Chipset Downlink"?

In that image, AMD directly allots 4 PCIe lanes to the chipset. So doesn't AMD have DMI bus or PCH? or something similar?

 

[rocktalkrock]

"4x Chipset Downlink" is just the 4 PCIe lanes to the chipset. 16 lanes from the CPU to the graphics slot and 4 lanes from the CPU to the chipset, for a total of 20. DMI bus and PCH are terms only used by Intel.

 

[Rdslw]

to sum up.
you have x16 git GPU
1x4 NVME direct to cpu
1x4 to chipset shared between 2x4 nvme(or 8 sata) + 4 sata + USB ports.
THAT's why its written as 16+4+4
PCIe
4.0 16+4+4