News Intel: 3nm Node Meets Yield and Performance Targets

[Admin]

Intel's datacenter-oriented process technology meets critical defect density and performance targets, the company says.

Intel: 3nm Node Meets Yield and Performance Targets : Read more

 

[bit_user]

So, a few weeks ago, there was some rumor of Arrow Lake getting fabbed on Intel 3 (instead of 20A). I took that to mean the CPU cores tile, but it wasn't clear. Is there some other tile in Arrow Lake that would make sense to fab on Intel 3, aside from the CPU and GPU tiles?

Regardless, it'll be exciting to see how Granite Rapids matches up against the Zen 5 EPYC, next year. I think it's meant to have up to 12 channels of MCR DDR5 DIMMs, so Intel is also scaling up bandwidth to feed the beast.

 

[everettfsargent]

Someone please wake me up when they have shipping and independent review of whatever products they actually release on any process technology. Thanks in advance.

 

[InvalidError]

So, a few weeks ago, there was some rumor of Arrow Lake getting fabbed on Intel 3 (instead of 20A).

The rumors I've seen say either TSMC N3 or Intel 20A. And I doubt anything besides CPU and GPU tiles would be made on the most advanced processes available since IO and cache have more or less hit the scaling ceiling.

 

[dramalamadingdong]

Man, I love Tom's Hardware. Been lurking for years and wanted to say so. Comments are an insightful riot. Peace and love baybee and electrons.

 

[alan81]

I interpreted the Intel comment a bit differently. They have been attempting to be more transparent, and as a result providing more internal data. I believe what they meant was Intel_3 met the goals they set for Q2 of 2023, not the overall end goals of the project. Intel will have a plan for incremental improvement each quarter, and all they are reporting is they are still on track to that plan. The comment "is on track for overall yield and performance targets" gives this away. At least this is my interpretation, which seems a bit different than the headline.

 

[The Historical Fidelity]

The rumors I've seen say either TSMC N3 or Intel 20A. And I doubt anything besides CPU and GPU tiles would be made on the most advanced processes available since IO and cache have more or less hit the scaling ceiling.

I’ve heard that the GPU tiles will be manufactured on TSMC N3 leaving at least the CPU tiles to be manufactured on Intel 20A. GPU wise, I believe all GPU tiles in the future will be on TSMC as well, since the discrete graphics architectures will all be TSMC products (doesn’t make sense to port their GPU designs on 2 separate incompatible nodes) and these tiles are just cut-down versions of said discrete designs.

 

[thisisaname]

Intel's 3nm-class process technology has met its defect density and performance targets, the company announced this week. The Intel 3 fabrication technology is on track to be used for high-volume manufacturing of Intel's upcoming codenamed Granite Rapids and Sierra Forest processors next year, according to Intel.

"Intel 3 met defect density and performance milestones in Q2, released PDK 1.1, and is on track for overall yield and performance targets," said Pat Gelsinger, chief executive of Intel, at the earnings call with analysts and investors. "We will launch Sierra Forest in the first half of 2024 with Granite Rapids following shortly thereafter, our lead vehicles for Intel 3."

It would be interesting to know how good those figures are, a lot can be improved in a year, to me it would seem the node is far from ready and much could go wrong.

 

[Kamen Rider Blade]

Why aren't client products using Intel 3?

 

[Unolocogringo]

Why aren't client products using Intel 3?

My understanding of the matter is yields are still too low.
So instead of making $100-$500 processors they are making $3000-$12,000 processors.
A few less dies per wafer but much higher $/mm² return to make them profitable.
Once yields are much better we might see client processors.

 

[bit_user]

I’ve heard that the GPU tiles will be manufactured on TSMC N3 leaving at least the CPU tiles to be manufactured on Intel 20A.

I think we've known that for a long time. I might try to go back and find the article, because it clearly said something got switched to Intel 3.

Anyway, unless it was the CPU tile, it's probably not worth thinking about. If it were the CPU tile, that would be big news, but then Intel couldn't just gloss over it, like they did in this announcement.

GPU wise, I believe all GPU tiles in the future will be on TSMC as well, since the discrete graphics architectures will all be TSMC products (doesn’t make sense to port their GPU designs on 2 separate incompatible nodes) and these tiles are just cut-down versions of said discrete designs.

Oh, but the tGPU tiles aren't just scaled down versions of their dGPUs! There was an interview with someone from Intel, a few months ago, who said one thing they've learned was that it's too costly to maintain like 3-4 different GPU designs, based on the product segment. The suggestion was that Arrow Lake is still a bespoke LP design, but possibly some later tGPU would be cut from the very same cloth as their dGPUs.

 

[The Historical Fidelity]

I think we've known that for a long time. I might try to go back and find the article, because it clearly said something got switched to Intel 3.

Anyway, unless it was the CPU tile, it's probably not worth thinking about. If it were the CPU tile, that would be big news, but then Intel couldn't just gloss over it, like they did in this announcement.


Oh, but the tGPU tiles aren't just scaled down versions of their dGPUs! There was an interview with someone from Intel, a few months ago, who said one thing they've learned was that it's too costly to maintain like 3-4 different GPU designs, based on the product segment. The suggestion was that Arrow Lake is still a bespoke LP design, but possibly some later tGPU would be cut from the very same cloth as their dGPUs.

Send me a link to that interview if you can, doesn’t match my friends insider info…if he is giving bad info “I’ll shove the interview in his face” sort of speak

 

[Amdlova]

I think intel will use Tsmc to make gpu. Take a piece of tsmc driving higher prices of the node forcing AMD to pay higher on the new nodes.

 

[thestryker]

So, a few weeks ago, there was some rumor of Arrow Lake getting fabbed on Intel 3 (instead of 20A). I took that to mean the CPU cores tile, but it wasn't clear. Is there some other tile in Arrow Lake that would make sense to fab on Intel 3, aside from the CPU and GPU tiles?

I think that rumor was saying TSMC N3 not Intel 3 for the shift, and that obviously was never going to happen. I think GPU tiles will probably be made at TSMC for the next few years as Intel depreciates 14nm and 10nm lines.

Regardless, it'll be exciting to see how Granite Rapids matches up against the Zen 5 EPYC, next year. I think it's meant to have up to 12 channels of MCR DDR5 DIMMs, so Intel is also scaling up bandwidth to feed the beast.

I'm curious about core density here, but they ought to have memory bandwidth on lock. Granite Rapids is going to be the first with MCR DIMM support and have already shown it in action. I doubt MRDIMMs are going to be ready for the first gen of Zen 5 server CPU so while I'd bet on AMD still having core density they won't be able to compete on memory bandwidth.

 

[bit_user]

Send me a link to that interview if you can, doesn’t match my friends insider info…if he is giving bad info “I’ll shove the interview in his face” sort of speak

Here's what I was remembering:

"There is a Xe and there is a Xe 2 and in that Xe 2 generation there is a Xe-LPG and there is a HPG (…) and there a slight variations (…) which is our big learning," said Tom Peterson, an Intel Fellow, in an interview with Hardwareluxx. "The idea was we needed to optimize for each segment and build separate chips and do separate verifications. And I think now the real learning is we would be better off concentrating our focus and really thinking of it like a really solidly, hard IP business."

On its Battlemage generation of GPUs, Intel will stick to Xe2-LPG and Xe2-HPG microarchitectures.

Intel's Talks Next-Gen GPUs: Xe2-HPG and Xe2-LPG

Simplifying development with fewer microarchitectures

www.tomshardware.com

I know Meteor Lake is still Alchemist-generation and I'm pretty sure so is Arrow Lake's! I can try to find a source on that, if you require it. I think that was one of those "Linked In" leaks.

 

[bit_user]

I think that rumor was saying TSMC N3 not Intel 3 for the shift, and that obviously was never going to happen. I think GPU tiles will probably be made at TSMC for the next few years as Intel depreciates 14nm and 10nm lines.

Here's what I think I saw. I don't remember which site I read it on:

Intel Arrow Lake CPUs Rumored To Drop 20A Node, Utilizing TSMC 3nm Instead

Intel is rumored to have canned its 20A process node launch with next-gen Arrow Lake CPUs and now going to utilize TSMC's 3nm node.

wccftech.com

I assume Intel would've at least alluded to that, in this announcement, if it were true.

I'm curious about core density here, but they ought to have memory bandwidth on lock. Granite Rapids is going to be the first with MCR DIMM support and have already shown it in action. I doubt MRDIMMs are going to be ready for the first gen of Zen 5 server CPU so while I'd bet on AMD still having core density they won't be able to compete on memory bandwidth.

AMD has its 3D V-Cache and they're dabbling with HBM in the MI300. So, they could surprise us with something we haven't seen yet, or perhaps they could simply include 3D V-Cache as standard, for the higher core-count Zen 5 EPYC models.

AMD has long shown an appreciation for the importance of memory bandwidth. I'd expect they're working to meet the needs Zen 5 will have.

 

[thestryker]

Here's what I think I saw. I don't remember which site I read it on:

​

Intel Arrow Lake CPUs Rumored To Drop 20A Node, Utilizing TSMC 3nm Instead

Intel is rumored to have canned its 20A process node launch with next-gen Arrow Lake CPUs and now going to utilize TSMC's 3nm node.

wccftech.com

​

I assume Intel would've at least alluded to that, in this announcement, if it were true.

Absolutely they'd have had to.

AMD has its 3D V-Cache and they're dabbling with HBM in the MI300. So, they could surprise us with something we haven't seen yet, or perhaps they could simply include 3D V-Cache as standard, for the higher core-count Zen 5 EPYC models.

It's hard to say what all we'll see HBM wise, but if it's cost viable I wouldn't be surprised if they did it. The results for certain workloads on SPR when you can stay within the HBM capacity is pretty crazy. I don't think they'd make 3DV standard, but I think they might try to ensure the SKUs are ready on launch instead of after.

AMD has long shown an appreciation for the importance of memory bandwidth. I'd expect they're working to meet the needs Zen 5 will have.

Right now we're in a circumstance where the core counts are getting so high properly parallelized workloads can sometimes use anything they can get. There will always be those edge cases that just need it all and the company delivering highest bandwidth and memory density will win there. I'll bet that with a 12 channel bus Intel will have the same issue with 2DPC motherboards AMD has had simply due to the large amount of room DIMMs take up. AFAIK there is zero capacity benefit to MCR so it'll be a purely bandwidth difference separating the two.

 

[NinoPino]

Hi Anton. I'm afraid to say that imho the article is full of mistakes and inaccurancies.
Starting with the titles, you write of a 3nm process but Intel have no 3nm in his roadmap and below in the article you talk of Intel 3 or Intel 3nm-class, so I think the title should refer to 7nm+.
Also referring to "Intel 3" process as a "3nm class" process is wrong. Neither Intel marketing ventured in such risky assumption.
Going on you write "Intel 3 (previoualy known as 5nm)" but it was 7nm enhanced SuperFin, not 5nm.
Again, all over the article you refer to 7nm+ as 3nm-class.
In the final you close the article writing that Intel 20A is a 20 Angstrom when instead is a 5nm process.

 

[alan81]

Hi Anton. I'm afraid to say that imho the article is full of mistakes and inaccurancies.
Starting with the titles, you write of a 3nm process but Intel have no 3nm in his roadmap and below in the article you talk of Intel 3 or Intel 3nm-class, so I think the title should refer to 7nm+.
Also referring to "Intel 3" process as a "3nm class" process is wrong. Neither Intel marketing ventured in such risky assumption.
Going on you write "Intel 3 (previoualy known as 5nm)" but it was 7nm enhanced SuperFin, not 5nm.
Again, all over the article you refer to 7nm+ as 3nm-class.
In the final you close the article writing that Intel 20A is a 20 Angstrom when instead is a 5nm process.

Keep in mind there really isn't any 10nm, 7nm, or smaller process in the world. The smallest feature on the TSMC N3 is around 20nm. Both TSMC and INTC have stopped using the "nm" designator, and while Intel has said the "A" stands for angstrom, they do not call it a 20 Angstrom process. The technical data shows Intel_4 has tighter geometries than TSMC N5, but not as tight as TSMC N3, so Intel_4 looks like a pretty good name. Intel is pretty much following the numbering scheme that TSMC has been using. The TSMC number has no relationship to a physical reality, but rather they just decrement the number when they introduce a new process. I have yet to see any technical data on either Intel_3 or Intel_20A in order to compare them to TSMC, however we do know both Intel_20A and TSMC N2 will be the first to use gate all around technology.

 

[InvalidError]

Keep in mind there really isn't any 10nm, 7nm, or smaller process in the world. The smallest feature on the TSMC N3 is around 20nm.

Depends on what you call a feature. If we're talking single individual detail size, Intel's 14nm FinFET process already featured 8nm-wide fins with ~8nm thick gate oxide laye on a 42nm fin-to-fin pitch. That is 10.5nm average feature size for the "14nm" FinFET cross-section.

 

[bit_user]

Starting with the titles, you write of a 3nm process but Intel have no 3nm in his roadmap and below in the article you talk of Intel 3 or Intel 3nm-class, so I think the title should refer to 7nm+.

It's fair for the article to talk about the process node using Intel's name for it. To do otherwise would cause confusion.

When using terms like "3nm-class", they're relating it to comparable process nodes from TSMC and Samsung. Everyone who knows anything about the subject knows these aren't truly 3 nm nodes.

Going on you write "Intel 3 (previoualy known as 5nm)" but it was 7nm enhanced SuperFin, not 5nm.

Are you sure about that? The only time I've seen Enhanced SuperFin was in relation to the 10 nm node that later got renamed to Intel 7.

Depends on what you call a feature. If we're talking single individual detail size, Intel's 14nm FinFET process already featured 8nm-wide fins with ~8nm thick gate oxide layer on a 42nm fin-to-fin pitch.

The fins are not themselves formed via lithography, but instead a chemical process. You couldn't therefore accurately call it 8nm lithography.

 

[alan81]

Depends on what you call a feature. If we're talking single individual detail size, Intel's 14nm FinFET process already featured 8nm-wide fins with ~8nm thick gate oxide laye on a 42nm fin-to-fin pitch. That is 10.5nm average feature size for the "14nm" FinFET cross-section.

Good point... I really meant "printed" feature. I see it a little like the old days when the process "number" was the printed poly width. When some companies had a hard time keeping up they switched to channel length, which allowed them to subtract the source/drain under diffusion from the poly width. When you are doing something with either registration or etch backs, you can get "features" that are much smaller than what lithography can print. Given both Intel_7 and TSMC N7 use 193nm wavelength light it is surprising how small some of the "features" are. My main point was that for both TSMC and INTC the process number is just a name and has nothing to do with the process itself. We need to look at the technical data on what the process achieved in order to compare them. As an aside, the Intel 10nm process was the last to meet the original IRTS definition for a 10nm process. TSMC deviated from the standard over a decade ago.

 

[InvalidError]

The fins are not themselves formed via lithography, but instead a chemical process. You couldn't therefore accurately call it 8nm lithography.

What part of lithography isn't a chemical process? Not much besides the mechanical handling between process steps.

Lithography itself is the process of depositing a photo-resist layer, exposing it to cure the parts you want to protect (or the other way around if using a negative photo-resist), using a solvent to remove the non-cured photo-resist, etching whatever was exposed to the desired depth, using another solvent to remove the cured photo-resist before depositing the next layer material and doing the whole thing all over again for each material layer.

The only thing special about FinFET is manipulating the etch steps to achieve straight fin walls since etching mushrooms out under the photo-resist when etching deeper than wide.

 

[bit_user]

What part of lithography isn't a chemical process?

My point is that they're not optical features. Their size isn't derived from a proportionally small feature in the masks.

 

[NinoPino]

It's fair for the article to talk about the process node using Intel's name for it. To do otherwise would cause confusion.

But the titles does not use the Intel process node name, that is "Intel 3". In the titles is written 3nm, and as you also confirm is wrong.

When using terms like "3nm-class", they're relating it to comparable process nodes from TSMC and Samsung. Everyone who knows anything about the subject knows these aren't truly 3 nm nodes.

I know, but Intel's name is "Intel 3" not "Intel 3nm-class". So calling 3nm-class is a choice of Anton, not a fact. May be someone can compare it with TSMC N3 and is a 3nm-class or compare with TSMC N4 so it is a 4nm-class, with Samsung, and so on. Imho this is not a fact but a personal choice.

Are you sure about that? The only time I've seen Enhanced SuperFin was in relation to the 10 nm node that later got renamed to Intel 7.

The source is the link in the article that point to another article of Tom's Hardware (Paul Alcorn).