Intel Announces 48-Core Cascade Lake-AP, Xeon E-2100 Processors

[chris.groups]

So the mighty Intel has basically had to copy tiny AMD's package design after ridiculing it earlier press calls.

 

[Olle P]

Fine print. 48 core vs 32 core Epyc (with SMT disabled)...

With that benchmark SMT is better disabled. Results get worse with SMT active.
The choice of benchmark does suggest that HT isn't even available on the Xeon though.

HT can be absent both to reduce TDP and to provide security, looking at the latest slew of vulnerabilities found.