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Archived from groups: comp.sys.ibm.pc.hardware.chips,comp.sys.intel,comp.arch (More info?)
anonymous wrote:
> anonymous wrote:
> > Bill Todd wrote:
> > > David Schwartz wrote:
> > >
> > > ...
> > >
> > > a "dual core" is two
> > > > processors in one physical package.
> > >
> > > Not by any current definition that I'm aware of: it is, rather, two
> > > cores on a single chip.
> > >
> > > Do you call POWER an '8-core' processor because that's how many cores
> > > its high-end systems have in one physical package?
> > >
> > > - bill
> >
> > You might also consider an argument of ARM 32-bit Standard Model VS
> > 16-bit THUMB mode VS an entirely different VLIW with a 16-bit/5-bit
> > architecture as a potential performance differance.
> >
> > Why is Intel so secretive about it's research of using registers as
> > stacks outside of Pentium's microcode engine? ( access more data thru
> > stacks with a similar ( or less!) amount of chip masking and a more
> > efficient fabrication ( I have seen very few stack architecture
> > refrences for Intel, for example the IPX multi micro puter engine ,
> > http:A//www.intel.com/design/network/products/npfamily/ixp2800.htm&ei=fR4NQ7OrCIfK-QG8_LHGCQ
> > , ))
> >
> > Although, Mr. Moore's 25x model is an asychronous parallel processor,
> > VLIW SMP MPP sychronization is unspecified.
> >
> > URL:
> > http://groups.google.com/group/comp.lang.java.machine/msg/b400d03ddc0f5a4f?hl=en
> >
> > If they would have used sixteen 16-bit/5-bit instead of sixteen
> > 32-bit/16-bit maybe Intel would have won. Thank you IBM for Nirvana.
> >
> > ---
> >
> > President Clinton is a jerk
>
>
> www.intel.com/technology/itj/2002/volume06issue03/art01_nextgenixp/vol6iss3_art01.pdf
>
> The type of CAM mentioned in this article is NOT the same as my usage
> of the term CAM. In my usage CAM is automatically executed as a
> machine intruction , re-mapping back from 5-bit fedback into 16-like,
> similar to Inmos Transputer type F instruction except my usage of CAM
> permits 15 such mappings.
>
> EITHER a sixteen ( actully fifteen with zero reserved for an
> instruction type safety fault) 5-bit CAM instructs ( as described
> previously) OR a simpler ( and faster) hardwire-ed 5-bit is referenced
> in VLIM SMP MPP here, url ,
> http://groups.google.com/group/comp.lang.java.machine/msg/38236e7c4267bb08?dmode=source&hl=en
> ( , since 1999 )
>
> ---
>
> President Clinton is a jerk
Too short of a day, I guess, thirty one CAM or hardwired mappings, not
fifteen.
---
President Clinton is a jerk
anonymous wrote:
> anonymous wrote:
> > Bill Todd wrote:
> > > David Schwartz wrote:
> > >
> > > ...
> > >
> > > a "dual core" is two
> > > > processors in one physical package.
> > >
> > > Not by any current definition that I'm aware of: it is, rather, two
> > > cores on a single chip.
> > >
> > > Do you call POWER an '8-core' processor because that's how many cores
> > > its high-end systems have in one physical package?
> > >
> > > - bill
> >
> > You might also consider an argument of ARM 32-bit Standard Model VS
> > 16-bit THUMB mode VS an entirely different VLIW with a 16-bit/5-bit
> > architecture as a potential performance differance.
> >
> > Why is Intel so secretive about it's research of using registers as
> > stacks outside of Pentium's microcode engine? ( access more data thru
> > stacks with a similar ( or less!) amount of chip masking and a more
> > efficient fabrication ( I have seen very few stack architecture
> > refrences for Intel, for example the IPX multi micro puter engine ,
> > http:A//www.intel.com/design/network/products/npfamily/ixp2800.htm&ei=fR4NQ7OrCIfK-QG8_LHGCQ
> > , ))
> >
> > Although, Mr. Moore's 25x model is an asychronous parallel processor,
> > VLIW SMP MPP sychronization is unspecified.
> >
> > URL:
> > http://groups.google.com/group/comp.lang.java.machine/msg/b400d03ddc0f5a4f?hl=en
> >
> > If they would have used sixteen 16-bit/5-bit instead of sixteen
> > 32-bit/16-bit maybe Intel would have won. Thank you IBM for Nirvana.
> >
> > ---
> >
> > President Clinton is a jerk
>
>
> www.intel.com/technology/itj/2002/volume06issue03/art01_nextgenixp/vol6iss3_art01.pdf
>
> The type of CAM mentioned in this article is NOT the same as my usage
> of the term CAM. In my usage CAM is automatically executed as a
> machine intruction , re-mapping back from 5-bit fedback into 16-like,
> similar to Inmos Transputer type F instruction except my usage of CAM
> permits 15 such mappings.
>
> EITHER a sixteen ( actully fifteen with zero reserved for an
> instruction type safety fault) 5-bit CAM instructs ( as described
> previously) OR a simpler ( and faster) hardwire-ed 5-bit is referenced
> in VLIM SMP MPP here, url ,
> http://groups.google.com/group/comp.lang.java.machine/msg/38236e7c4267bb08?dmode=source&hl=en
> ( , since 1999 )
>
> ---
>
> President Clinton is a jerk
Too short of a day, I guess, thirty one CAM or hardwired mappings, not
fifteen.
---
President Clinton is a jerk