[citation][nom]ojas[/nom]I'd only partially agree with you here. Intel plans their stuff very far out in the future. 22nm tri-gate stuff was in development since the 90's. iirc lithography was in the hundreds of nanometers then.So yeah...they may run into problems, but "in sight" is a believable statement.And 14nm Broadwell based chips ARE planned for 2014, 2013 will see Haswell, which is still 22nm.I mean, yes, according to the pure tick-tock cycle we should have an official haswell release by the end of this year, but i think it's lagged behind enough to make it just one iteration of the cycle per year.And in that sense 2014 is "in time" for Broadwell. They had already started manufacturing their fabs a few months ago, so i don't anticipate much delay. Probably launch around the same time frame as ivy did.Assuming that the one cycle per year holds, we'll have Skymont/Skylake in 2015/16 (can't remember the order) so 2016=10nm. Then 2018 should see 7nm, and 2020 should be the year for 5nm. So yeah off by a year at least as i see it (from 2019).BTW i wonder what would happen if you shrink the manufacturing process but keep the same die size...[/citation]
[citation][nom]article[/nom]Intel's manufacturing cadence suggests that the first 14 nm products will arrive in late 2013[/citation]
That's why I responded saying that I doubt that 14nm will hit in 2013. The article says that it should and I just don't see it.
I see your point in that I may have not thought to differentiate between "in sight" and "set in stone", my bad on that.
As for shrinking the process and keeping the same die size, well, unless clocks are dropped, that'd mean increased power consumption. A die shrink usually reduces area used by the CPU by very roughly 50% (increased IGP size might counteract this, but is irrelevant for CPU performance comparisons with the IGP disabled), but power consumption with the same or roughly the same architecture has been dropping by more like 30% at the same clock frequency. Unless Intel is setting the voltage too high, keeping the same die size with the same or roughly the same architecture and clock frequencies would likely mean a roughly 20-40% increase in power consumption.
Dropping clocks or some other sort of trick would be necessary to counteract the power consumption increase and them architectural improvements would be necessary to counter-act the performance impact of lower frequencies. Maybe instead of that, something such as AMD's High-Density Library could be used to counteract the power consumption hit instead of lowering frequencies, but architectural improvements would still be important for making a performance difference.
Shrinking the die with smaller processes is easier than doing any of this.