They have been one of TSMC's largest customers for many years now. With demand for all production capacity worldwide completely overwhelming this is the fastest way to grow. They have proven they have the ability to sell everything they can make now and probably quite a bit of what others can make for them. Just to maintain market share they have to add capacity.
All the major fabs are limited in how fast they can add capacity by how many machines/tools they can get from ASML.
The Xe-HPC compute tiles and Xe-HPG entire chip are reported to be built at TSM already. GPUs run pretty hot and take up a lot of room. I think Intel would use 3nm shrinks on these to get the space and power savings while holding performance the same. Intel can stack compute tiles on top of a different process io tile ... already demoed with Lakefield and in progress on Xe-HPC.
For the Xeon CPUs ... perhaps Intel is moving to large number of Atom tiles on some server chips as a direct response to Apple and other small core server solutions.
Also, the TSM hybrid bonding stacked SRAM appears to be ahead of Intel's hybrid bonding development, so perhaps 3NM tiles of stacked SRAM would give Intel an advantage over AMD's v-cache density. Makes sense.