Two questions, Jack: Intel supposedly is introducing both MCM (Yorkfield) and monolithic-die quad-core CPUs (Wolfdale) on the 45nm process using the same micro-architecture while an 8-core CPU is not on the roadmap. If the FSB isn't a problem for shuffling data between the two core banks, why go through the expense of making a new die mask and getting the slightly lower yields of chips? Or do you think there will be enhancements like a shared L3 cache for all the cores that requires a monolithic die like the K8L?
The currently slated quad core from what I have read is Yorksfield, some sites have stated it is monolithic, others MCM --- makes not much difference really other than a monolithic of course avoids the snoop contention over the bus. There is onething about the core uArch and the MCM approach --- since cache is shared, from a coherency point of view, there is not much difference in that only two caches must cohere. The roadmap is kinda merky when it comes to Intel's plans past Penryn, we know of Nehalem, and we also hear that Nehalem will integrate the memory controller as well as support CSI, this is likely where the monolithic quad will play in.... for the very reasons you state.
The MCM approach has two distinct advantages and one distinct disadvantage. The disadvantage is already out --- the snoop and coherency across the FSB. The two advantages are of course well known too and you mentioned it -- time to market and yield. I don't think Intel will move to a monolithic core before the end of 2007 on the current architecture, but that remains to be seen. One thing though that there is not clear answer --- will the FSB bottleneck a quad core Penryn derivative. We don't know --- the FBS will jump to 1333 MHz, giving a full 10.5 GB/sec BW to the socket, but the clock speed of the processor will also scale up, reportedly to 3.5-3.7 GHz. 333 is 33% icnrease but so is the rumored release speed (slightly over 33%). So scaling wise, there should be no difference in observed bottlenecks than what we observe for stock Kentsfield on a quad --- which is none.
All in all it will be a wait and see game.... I am working now to find the FSB limitations on the current quad, and once I find that point I can give you a more reasonable estimate. But to answer your questions, the monolithic quad core design is not on the horizon at least not from any clear cut roadmap and 2nd, the next major revision with the IMC/CSI will do away with any debate about FSB issues.
What I wonder is if Intel will keep the large L2 cache with an IMC --- my guess is no, or if they do, there will be a larger gradation of different cache sizes to choose from...
EDIT: If you are looking for what might be exciting or novel from Intel this year....
- Watch 45 nm, the rumor mill is amiss with high-k, if this is true AMD will not hold the performance crown in 2007 and we will need to look to 2008 for what migh be competitive against Nehalem. But with an IMC and the BW that goes with that, well, AMD has their work cut out for them.... it will be interesting.
- I would not be surprised if Intel cuts in a dual FSB on the high end Bearlake chipset and produces a dual socket workstation/DT MB in the same vain as AMD's 4x4 -- just to keep up with the core race as AMD will tout 8 cores on the board when barcelona hits. This is purely speculation... however, they already know how to do it as broadwater already employees a 64 meg Snoop filter chipset with dual FSBs, I could see a DT variety with say a 32 Meg or 16 Meg snoop filter and dual FSBs.
Jack
Any guess if there will be some 1066 fsb yorkfield and if the p965 can run at 1333 (with a 1333 cpu)?