News Intel Will Adopt 3D Stacked Cache for CPUs, Says CEO Pat Gelsinger

[Admin]

Intel CEO Pat Gelsinger said that Intel will adopt 3D stacked caches that are similar to AMD's approach with its 3D V-Cache processors.

Intel Will Adopt 3D Stacked Cache for CPUs, Says CEO Pat Gelsinger : Read more

 

[imsurgical]

It's logical that Intel could adopt this sort of technology; the hybrid bonding technology behind 3D V-Cache isn't proprietary to AMD. Additionally, this sort of chip architecture has been on the long-term horizon for chip makers for several years.

Can definitely feel the defensive posture in this one from the writer. I don't recall, but when AMD did utilize it, did you guys say anything commendable, or at least stand out? You know, being around for several years and all? 🙄🤷‍♂

 

[PaulAlcorn]

Can definitely feel the defensive posture in this one from the writer. I don't recall, but when AMD did utilize it, did you guys say anything commendable, or at least stand out? You know, being around for several years and all? 🙄🤷‍♂

I've given editor's choice awards to nearly every X3D CPU. It's game-changing tech, quite literally, and a staple on our list of Best CPUs.

 

[spongiemaster]

Can definitely feel the defensive posture in this one from the writer. I don't recall, but when AMD did utilize it, did you guys say anything commendable, or at least stand out? You know, being around for several years and all? 🙄🤷‍♂

AMD didn't have anything to do with developing the 3d stacking technology behind 3D Vcache. It was developed by TSMC and AMD just used it. What should AMD get credit for?

TSMC's announcement of 3D stacking from 2018:

TSMC Announces Wafer-on-Wafer 3D Stacking Technology

TSMC is announcing that they have a new Wafer-on-Wafer 3D stacking technology. Just don’t expect it to show up on GPUs any time soon.

www.eteknix.com

Any mention of AMD in that? AMD announced 3D VCache in 2021.

 

[PaulAlcorn]

AMD didn't have anything to do with developing the 3d stacking technology behind 3D Vcache. It was developed by TSMC and AMD just used it. What should AMD get credit for?

TSMC's announcement of 3D stacking from 2018:

TSMC Announces Wafer-on-Wafer 3D Stacking Technology

TSMC is announcing that they have a new Wafer-on-Wafer 3D stacking technology. Just don’t expect it to show up on GPUs any time soon.

www.eteknix.com

Any mention of AMD in that? AMD announced 3D VCache in 2021.

Yes, I've written about the innumerable times. That is why I mention it is not AMD proprietary tech.

AMD Shares New Second-Gen 3D V-Cache Chiplet Details, up to 2.5 TB/s

New images of the I/O Die, too.

www.tomshardware.com

I added that link to the article to make it more clear.

 

[hotaru251]

you're talking about a very specific technology that TSMC does with some of its customers

he really just refuses to say AMD...

 

[kwohlt]

Can definitely feel the defensive posture in this one from the writer. I don't recall, but when AMD did utilize it, did you guys say anything commendable, or at least stand out? You know, being around for several years and all? 🙄🤷‍♂

Seems more to preemptively explain to people that the inevitable "Intel is copying AMD!" comments are unfounded, and that it's rather a breakthrough technology that TSMC beat Intel to maket

 

[Alvar "Miles" Udell]

Being second to a market isn't necessarily a bad thing. Intel now knows where 3D cache chips will bring their benefits, and AMD is still essentially refining 3D cache to eliminate its drawbacks, which they haven't quite done yet.

 

[bit_user]

Now that you mention it... given how long Intel has been banging on about Foveros, it's rather surprising that AMD managed to release at least two generations of 3D V-Cache before Intel has even managed one!

I wouldn't be surprised if AMD is on their 3rd gen V-Cache, by the time Intel has anything comparable on the market. All of that experience will hopefully serve AMD well, in terms of things like negotiating the apparent thermal issues, etc.

Being second to a market isn't necessarily a bad thing. Intel now knows where 3D cache chips will bring their benefits, and AMD is still essentially refining 3D cache to eliminate its drawbacks, which they haven't quite done yet.

So, you're essentially betting that Intel knocks it out of the park, on their first time at bat? If you just look at the amount of improvement between Alder Lake and Raptor Lake, you can see that even the mighty Intel doesn't get everything perfect on the first try! And Alder Lake wasn't even their first hybrid CPU - that distinction belongs to Lakemont!

 

[Kona45primo]

It's about darn time. Intel has finally figured out they cannot compete with TSMC. They will soon be on a level playing field with AMD. Let the best engineered chip win and I hope it's a knock down drag out fight. Competition = innovation & cut throat pricing

 

[salgado18]

Now that you mention it... given how long Intel has been banging on about Foveros, it's rather surprising that AMD managed to release at least two generations of 3D V-Cache before Intel has even managed one!

I wouldn't be surprised if AMD is on their 3rd gen V-Cache, by the time Intel has anything comparable on the market. All of that experience will hopefully serve AMD well, in terms of things like negotiating the apparent thermal issues, etc.


So, you're essentially betting that Intel knocks it out of the park, on their first time at bat? If you just look at the amount of improvement between Alder Lake and Raptor Lake, you can see that even the mighty Intel doesn't get everything perfect on the first try! And Alder Lake wasn't even their first hybrid CPU - that distinction belongs to Lakemont!

Usually I would agree, but the first gen Intel GPU has great raytracing to raster performance, much better than AMD's second gen attempt. Maybe tons of money can make some miracles?

 

[bit_user]

Usually I would agree, but the first gen Intel GPU has great raytracing to raster performance, much better than AMD's second gen attempt. Maybe tons of money can make some miracles?

It's true that Intel's Alchemist did better on the Ray Tracing & Deep Learning fronts than it did on raster performance. Perhaps they expected those two to be hard and put the appropriate investment there, while underestimating raster because their iGPUs had been doing it for so long they assumed it would be a lot more straight-forward?

Something else to consider: I think both ray tracing and deep learning have a lot more to do with how much die area they wanted to devote to those tasks, since their performance is dominated by hard-wired circuitry, whereas raster performance involves more complex aspects of programmable shader performance.

However, Intel is a big company and the dGPUs were designed in a totally different business unit. I think you really can't apply the track record of one team towards predicting the future of another, who are working on something very different.

 

[spongiemaster]

Yes, I've written about the innumerable times. That is why I mention it is not AMD proprietary tech.

AMD Shares New Second-Gen 3D V-Cache Chiplet Details, up to 2.5 TB/s

New images of the I/O Die, too.

www.tomshardware.com

I added that link to the article to make it more clear.

Sorry, that wasn't directed to you. Your post wasn't visible when I started responding to imsurgical.

 

[bit_user]

AMD didn't have anything to do with developing the 3d stacking technology behind 3D Vcache. It was developed by TSMC and AMD just used it. What should AMD get credit for?

Because making 3D V-Cache work well involves a lot more than just mashing two dies atop each other! You have to adapt your cache architecture and the floorplan of your compute die properly, in order for it to deliver the kinds of benefits we observed. That's AMD's contribution.

Chips & Cheese did some detailed profiling of 3D V-Cache and was surprised at how little latency the enlargement added:

Deep Diving Zen 3 V-Cache

This is the deeper dive of AMD’s V-Cache that we teased with our short latency article and we will be covering a little more on the latency front along with the bandwidth behavior of V-Cache and the performance of V-Cache SKUs.

chipsandcheese.com

SemiAnalysis noted just how much it seemed to have influenced the layout of Zen 4, when comparing it vs. Zen 4C (which eliminated the TSVs used to attach 3D V-Cache):

Zen 4c: AMD’s Response to Hyperscale ARM & Intel Atom

Bergamo Volumes, ASP, Performance, Hyperscale Order Shift, Die Shot, Floorplan, Physical Design, and Future Use of Dense Core Variants Bergamo, AMD’s upcoming 128-core server part sets new heights …

www.semianalysis.com

Elsewhere, probably during the launch coverage of the 7950X3D, I read about how AMD engineered the N7 cache die to achieve higher SRAM density than they apparently even managed on their N5 CCD, as well as how they carefully engineered placement and overhang vs. the cores. I'll post a link, if I can find it.

In short, I consider it a neat "division of labor" story.

 

[vertuallinsanity]

AMD didn't have anything to do with developing the 3d stacking technology behind 3D Vcache. It was developed by TSMC and AMD just used it. What should AMD get credit for?

AMD has formidable design chops, fwiw.

Chip-on-wafer was designed by AMD and implemented by TSMC on 3d cache cpus.

Wafer-on-wafer is a TSMC design.

 

[spongiemaster]

AMD has formidable design chops, fwiw.

It isn't worth all that much in the grand scheme of things. Having good ideas is a universe away from producing a commercially viable product. AMD dumped their fabs when they couldn't afford them any more. Then GloFo ended up quitting leading edge node development when they couldn't get 7nm right. If GloFo didn't let AMD out their contracts at that point, AMD would be dead and buried. Without TSMC storming into the lead, AMD isn't where they are today. Without TSMC developing 3d stacking, AMD doesn't have 3D V cache. They would not have come up with that on their own, and they obviously couldn't manufacture it with GloFo.

 

[DaveLTX]

Because making 3D V-Cache work well involves a lot more than just mashing two dies atop each other! You have to adapt your cache architecture and the floorplan of your compute die properly, in order for it to deliver the kinds of benefits we observed. That's AMD's contribution.

Chips & Cheese did some detailed profiling of 3D V-Cache and was surprised at how little latency the enlargement added:

​

Deep Diving Zen 3 V-Cache

This is the deeper dive of AMD’s V-Cache that we teased with our short latency article and we will be covering a little more on the latency front along with the bandwidth behavior of V-Cache and the performance of V-Cache SKUs.

chipsandcheese.com

​

SemiAnalysis noted just how much it seemed to have influenced the layout of Zen 4, when comparing it vs. Zen 4C (which eliminated the TSVs used to attach 3D V-Cache):

​

Zen 4c: AMD’s Response to Hyperscale ARM & Intel Atom

Bergamo Volumes, ASP, Performance, Hyperscale Order Shift, Die Shot, Floorplan, Physical Design, and Future Use of Dense Core Variants Bergamo, AMD’s upcoming 128-core server part sets new heights …

www.semianalysis.com

​

Elsewhere, probably during the launch coverage of the 7950X3D, I read about how AMD engineered the N7 cache die to achieve higher SRAM density than they apparently even managed on their N5 CCD, as well as how they carefully engineered placement and overhang vs. the cores. I'll post a link, if I can find it.

In short, I consider it a neat "division of labor" story.

To be fair, Zen 4 is aimed at way higher clockspeeds compared to Zen 3 thus the sram density.
And N5 doesn't really scale significantly better than N7 at sram either

Zen 4 happily sits at north of 5ghz while Zen 3 struggles to hit 5
If N7 scaled better they would have dedicated the area on Zen 3 to clock higher but they were working to decrease area for the sake of efficiency.

 

[DaveLTX]

It isn't worth all that much in the grand scheme of things. Having good ideas is a universe away from producing a commercially viable product. AMD dumped their fabs when they couldn't afford them any more. Then GloFo ended up quitting leading edge node development when they couldn't get 7nm right. If GloFo didn't let AMD out their contracts at that point, AMD would be dead and buried. Without TSMC storming into the lead, AMD isn't where they are today. Without TSMC developing 3d stacking, AMD doesn't have 3D V cache. They would not have come up with that on their own, and they obviously couldn't manufacture it with GloFo.

AMD very much designed the Chip-On-Wafer when they were trying to mount memory close to the GPU! They worked with tsmc to make sure it could happen.

 

[hotaru251]

They will soon be on a level playing field with AMD.

not really.

Intel's using big/little.

AMD isnt there yet (if zen can scale in that...intels really f'd) & dont really know how well 3dcache will work with it either. (as dont think it can function for both big and little cores)

 

[jkflipflop98]

It's about darn time. Intel has finally figured out they cannot compete with TSMC. They will soon be on a level playing field with AMD. Let the best engineered chip win and I hope it's a knock down drag out fight. Competition = innovation & cut throat pricing

Oh please. Gag.

It's like you kids have forgotten the last 50 years.

 

[bit_user]

Intel's using big/little.

AMD isnt there yet (if zen can scale in that...intels really f'd) & dont really know how well 3dcache will work with it either. (as dont think it can function for both big and little cores)

Phoenix 2 is big.little and already shipping.

AMD Phoenix 2 Review Evaluates Zen 4, Zen 4c Performance

Ryzen Z1/Ryzen 5 7540U vs. Ryzen 7 7840U

www.tomshardware.com

Zen 4C doesn't support 3D V-Cache. That had to go, in order to make it more compact. Of course, in a Big.Little CPU, some or all of the big cores could still have 3D V-Cache.

 

[Lucky_SLS]

I see the same discussion that happened with a previous news article here XD

Page 2 - News - Intel's Core i9-14900K Shows Increased Multi-Threaded Performance in Leaked Benchmarks

Page 2 - Seeking answers? Join the Tom's Hardware community: where nearly two million members share solutions and discuss the latest tech.

forums.tomshardware.com

 

[Ravestein NL]

Being second to a market isn't necessarily a bad thing. Intel now knows where 3D cache chips will bring their benefits, and AMD is still essentially refining 3D cache to eliminate its drawbacks, which they haven't quite done yet.

But....
"Doing something differently" does not mean that it will be beter than the original. I don't know how Intel is going to work with 3D cache but it seems to me if they don't know TMSC's process exactly they probably are going to make the same mistakes (or encounter same problems) that TMSC had. To me as a technician that's a waste of time and effort. And "doing it differently", ofcourse, why set a standard?!

 

[TerryLaze]

But....
"Doing something differently" does not mean that it will be beter than the original. I don't know how Intel is going to work with 3D cache but it seems to me if they don't know TMSC's process exactly they probably are going to make the same mistakes (or encounter same problems) that TMSC had. To me as a technician that's a waste of time and effort. And "doing it differently", ofcourse, why set a standard?!

Why get sued or have to pay royalties?!

Also intel will put the compute tile on top of the cache, instead of cache on top the compute as ryzen does, which will probably make it easier to keep providing the same amount of cooling to the cores.

"but in our roadmap, you're seeing the idea of 3D silicon where we'll have cache on one die, and we'll have CPU compute on the stacked die on top of it,"

 

[Ravestein NL]

"but in our roadmap, you're seeing the idea of 3D silicon where we'll have cache on one die, and we'll have CPU compute on the stacked die on top of it,"

That's just what I mean. Who says that doing it that way will be better?
The cores may stay cooler but if the cache gets to hot it's throughput will go down.
Maybe it's an idea to have all connections on the side and cool the top and bottom part of a CPU with stacked silicon. Just a crazy idea.