News Intel's Arrow Lake chips may have lower clock speeds than previous CPUs — Core Ultra 9 QS achieves 5.7 GHz boost and 5.4 GHz across all P-cores

[Admin]

Arrow Lake clock speeds have been leaked, suggesting that the maximum clock speeds for Arrow Lake CPUs will be worse than Raptor Lake CPUs.

Intel's Arrow Lake chips may have lower clock speeds than previous CPUs — Core Ultra 9 QS achieves 5.7 GHz boost and 5.4 GHz across all P-cores : Read more

 

[King_V]

Agreed with the statement that clock speeds aren't the be-all and end-all.

If these things run lower clock speeds, but still perform better, and/or consume less power, then it's a good thing. Intel's been pushing this "MOAR HERTZES" for a bit too long, now. 12th gen was a nice step for them, but then they went brute force again after that.

I welcome this step.

 

[Amdlova]

When intel see the amd Benchmarks... nah downclock the cpus make it overclockable again..
Before amd fiasco they say will have 100w less than the old generation now? 150w less

 

[TheSecondPower]

This is hardly surprising. The 14k series is more or less 10nm+++++, a process which has had a chance to become very tuned for high clock speeds. It wasn't until 10nm+++ 10ESF Intel 7—about the fourth generation—that Intel's N7 competitor came to desktops. Candidates for manufacturing Arrow Lake-S include Intel 20A (brand new), Intel 3 (Intel 4+, about 9 months old), and TSMC N3B (N3E+, about 10 months old). It's doubtful that any of these could achieve the same clock speeds. But any will support more transistors at less power.

 

[usertests]

AMD hoping for a small enough increase to keep the lead with Zen 5 X3D (and fixed drivers).

 

[JRStern]

I'm in no freaking hurry. I don't need seriously more power than my ten year old desktop with 3.9ghz turbo but I'd like it fanless with integrated graphics, that Panther Lake chips sound good to me so far. Hopefully a few more cores, especially the e-cores, help keep power down and performance up. And the 20a, 18a, whatever, get the same performance and more for less power. Intel has been a power pig for way too long.

 

[The Historical Fidelity]

Agreed with the statement that clock speeds aren't the be-all and end-all.

If these things run lower clock speeds, but still perform better, and/or consume less power, then it's a good thing. Intel's been pushing this "MOAR HERTZES" for a bit too long, now. 12th gen was a nice step for them, but then they went brute force again after that.

I welcome this step.

Looks like Intel realized pushing way too much voltage through their cores to get to that 6.0 ghz number will bring nothing but pain and suffering 6 months after release.

 

[The Historical Fidelity]

This is hardly surprising. The 14k series is more or less 10nm+++++, a process which has had a chance to become very tuned for high clock speeds. It wasn't until 10nm+++ 10ESF Intel 7—about the fourth generation—that Intel's N7 competitor came to desktops. Candidates for manufacturing Arrow Lake-S include Intel 20A (brand new), Intel 3 (Intel 4+, about 9 months old), and TSMC N3B (N3E+, about 10 months old). It's doubtful that any of these could achieve the same clock speeds. But any will support more transistors at less power.

It’s interesting that this QS sample and AMD’s 9950x both top out at 5.7 GHz.

Also, call me thick headed but I have a big problem with Intel adopting a 10x measurement that is NOT an official SI measurement. Angstroms are rarely used in anything other than 3D conformation analyses of protein structures and atomic layouts. Let’s just call Intel 20A what it is, Intel 2….the semiconductor industry went from micrometers to nanometers which is a 1000x or 3 factor step, the logical step after this is picometers, not a 1 factor 10x half step like angstrom. Feels like Intel marketing had something to do with adopting this non-SI unit to fool laymen consumers . “Oh look Intel is in the Ångström era, Intel 20A must be better than TSMC’s old era 2nm.”

 

[froggx]

It’s interesting that this QS sample and AMD’s 9950x both top out at 5.7 GHz.

Also, call me thick headed but I have a big problem with Intel adopting a 10x measurement that is NOT an official SI measurement. Angstroms are rarely used in anything other than 3D conformation analyses of protein structures and atomic layouts. Let’s just call Intel 20A what it is, Intel 2….the semiconductor industry went from micrometers to nanometers which is a 1000x or 3 factor step, the logical step after this is picometers, not a 1 factor 10x half step like angstrom. Feels like Intel marketing had something to do with adopting this non-SI unit to fool laymen consumers . “Oh look Intel is in the Ångström era, Intel 20A must be better than TSMC’s old era 2nm.”

It's probably because once you hit 1 Angstrom you're below the atomic radius of silicon which is a hard limit on process node shrinks using our current physics. Realistically more like 2 Angstroms due to Van Der Waals forces. Doubt you can even go that small, but quantum physics and semiconductor manufacture aren't my specialties.

Something about 200ish picometers as a hard stop doesn't look that nice from a marketing view after everyone got used to sizes like 3nm.

 

[The Historical Fidelity]

It's probably because once you hit 1 Angstrom you're below the atomic radius of silicon which is a hard limit on process node shrinks using our current physics. Realistically more like 2 Angstroms due to Van Der Waals forces. Doubt you can even go that small, but quantum physics and semiconductor manufacture aren't my specialties.

Something about 200ish picometers as a hard stop doesn't look that nice from a marketing view after everyone got used to sizes like 3nm.

But a “1A” process is not 1 Ångström in size. It’s much bigger. For instance, the smallest features for a 2nm process is actually 20nm in size and 1nm is 16nm according to the IEEE. So we will be well into the picometer naming scheme before we hit the silicon monolayer theoretical limit.

 

[thestryker]

I'm in no freaking hurry. I don't need seriously more power than my ten year old desktop with 3.9ghz turbo but I'd like it fanless with integrated graphics, that Panther Lake chips sound good to me so far.

If Intel releases Skymont based parts as a replacement for ADL-N these could be perfect for that application. Passive boxes with sufficient cooling don't tend to happen for the full fledged laptop parts from my experience. My passive N305 based router box does pull up to 29W and doesn't overheat so it'd certainly be possible though.

 

[DavidC1]

But a “1A” process is not 1 Ångström in size. It’s much bigger. For instance, the smallest features for a 2nm process is actually 20nm in size and 1nm is 16nm according to the IEEE. So we will be well into the picometer naming scheme before we hit the silicon monolayer theoretical limit.

And they are never gonna reach anywhere near even 5nm except for the substructures. Substructures such as the gate dielectric has reached 1nm with the Intel 90nm generation(which they had to increase 3x by using High-K metal gates on 45nm to reduce gate leakage, so that's not 1nm either anymore).

Changes like FinFET, GAA, Nanosheets are all attempts to get the benefits without the shrink. Nanosheets and Nanowires are all about stacking and having multiple gates and channels in one device so actual physical scaling will stop completely at that point. Of course they'll say now you have TWO so you have twice the density, which from the mm2 standpoint is true, but now you have to have two layers so you aren't anywhere near reducing cost, which was the big point of "Moore's Law".

TSMC and Samsung started the node naming BS. 20nm was half the size of 28nm, but 16nm was basically 20nm + FinFET. After that the naming was basically worthless. Samsung is even worse of course. Variants of their "5nm" was really nothing but plus versions of their 7nm, even admitted in their own slides, and likely it underperformed TSMC's N7.

The last true process naming was with Intel 32nm. After that it's all nebulous marketing wizardry.

 

[The Historical Fidelity]

And they are never gonna reach anywhere near even 5nm except for the substructures. Substructures such as the gate dielectric has reached 1nm with the Intel 90nm generation(which they had to increase 3x by using High-K metal gates on 45nm to reduce gate leakage, so that's not 1nm either anymore).

Changes like FinFET, GAA, Nanosheets are all attempts to get the benefits without the shrink. Nanosheets and Nanowires are all about stacking and having multiple gates and channels in one device so actual physical scaling will stop completely at that point. Of course they'll say now you have TWO so you have twice the density, which from the mm2 standpoint is true, but now you have to have two layers so you aren't anywhere near reducing cost, which was the big point of "Moore's Law".

TSMC and Samsung started the node naming BS. 20nm was half the size of 28nm, but 16nm was basically 20nm + FinFET. After that the naming was basically worthless. Samsung is even worse of course. Variants of their "5nm" was really nothing but plus versions of their 7nm, even admitted in their own slides, and likely it underperformed TSMC's N7.

The last true process naming was with Intel 32nm. After that it's all nebulous marketing wizardry.

Thank you for the nice summary! Yes the naming schemes are arbitrary but contacted gate pitch and metal pitch are two variables that continue to shrink gen on gen. For example, IEEE predicted 5nm to be around 51nm gate pitch and 30nm metal pitch and TSMC N5 came out to being 51nm and 28nm respectively, then IEEE 3nm prediction was 48nm and 24nm respectively and TSMC came out being 48nm and 23nm respectively. There’s no TSMC public data for their N2 node but it should be close to IEEE’s prediction of 45nm and 20nm respectively.

Interestingly, it seems that metal pitch has a greater effect on density improvements compared to gate pitch as Samsung 3GAE process has smaller gate pitch than TSMC 3 at 40nm vs 48nm respectively but larger metal pitch at 32nm vs 23nm respectively resulting in a 150 MTr/mm^2 for Samsung and 215.6 MTr/mm^2 for TSMC.

 

[DavidC1]

Thank you for the nice summary! Yes the naming schemes are arbitrary but contacted gate pitch and metal pitch are two variables that continue to shrink gen on gen.

This is going to stop to a halt with nanosheets and nanowires. Because they'll get "density" by stacking.

View: https://www.youtube.com/watch?v=Qnl7--MvNAM


Look at starting at 14:44.

-Pitch Scaling: 2x, meaning 0.7x in each side or about 15nm.
-Nanowires 2x
-Stacked nanowire 2x
-Wafter to wafer
-Die to wafer

Starting with nanowire generation pitch scaling essentially drops to zero. So 15nm is the practical size for overall transistors. But we used to get 2x scaling by simply changing all structures by 0.7x. No worries about strained silicon(90nm) High-K dielectric(45nm), FinFET(22nm) and others that add cost and reduce the benefits.

Intel is saying 18A is a mere 15% per/watt and 30% density benefit over Intel 3. They also said 14A is another 15% perf/watt gain and disappointing 20% density gain. MORE work, LESS gain.

 

[The Historical Fidelity]

This is going to stop to a halt with nanosheets and nanowires. Because they'll get "density" by stacking.

View: https://www.youtube.com/watch?v=Qnl7--MvNAM


Look at starting at 14:44.

-Pitch Scaling: 2x, meaning 0.7x in each side or about 15nm.
-Nanowires 2x
-Stacked nanowire 2x
-Wafter to wafer
-Die to wafer

Starting with nanowire generation pitch scaling essentially drops to zero. So 15nm is the practical size for overall transistors. But we used to get 2x scaling by simply changing all structures by 0.7x. No worries about strained silicon(90nm) High-K dielectric(45nm), FinFET(22nm) and others that add cost and reduce the benefits.

Intel is saying 18A is a mere 15% per/watt and 30% density benefit over Intel 3. They also said 14A is another 15% perf/watt gain and disappointing 20% density gain. MORE work, LESS gain.

That’s in line with the IEEE prediction for 1nm being 40nm gate pitch and 16nm metal pitch.
Realistically stacking will only get us so far as eventually heat soak will limit the power that transistors in the lower and middle layers can handle before overheating. We would need to come up with a 3D cooling method to keep all layers at relatively the same temperatures.

However a lesser known, quite difficult to manufacture way to gain an impressive density increase without resorting to 3D stacking is to mount the gate vertically IE z-axis. The difficult part is that it must be a dual substrate sandwich, essentially etching the gate on one substrate (aka the male substrate) then building a female substrate that fits around and terminates all the gates. Then wiring these two substrates is a whole other mess.

It will be interesting to see what ingenuity comes out as the future unfolds.