Intel's New Factory to Make 450mm Chip Wafers

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JeanLuc, They sometimmes mess up a wafer. As the size gets larger the cost per 450mm, 500mm or 600mm wafer goes up. Also they have challanges as the wafers get bigger like vibrbational effecs, gravitatinal sagging, and creatinng perfectly flat wafers that large. So they slowly increase the sizes of wafers to get more bang for the buck when they learn how to deal with all of the challanges the larger sizes present.
 
[citation][nom]loomis86[/nom]Not exactly. They aren't pocketing the savings. They are spending it on more R&D for the next phase of improvements. They could sell cheaper but then the technology would advance at a slower rate and if it advances slow enough for the chinese to catch up...GAME OVER. The chinese can produce anything cheaper than we can once they learn how to make it.[/citation]
You, sir, deserve a cookie. I know that when I buy an expensive high end chip, I'm helping contribute to the next one. :)

I wonder how many chips they'll get out of a 450mm wafer.
I also wonder how much those giant pieces of pure silicon cost. I watched a video on the production of wafers starting from scratch once, and it was pretty cool.
 
i do not understand why intel chooses to build in earthquake country. the labor is cheaper there as well as taxes and other factors, but that would all get negated by the tremors they have all the time on the west coast.
must have been on heck of a sweet $$$ deal brokered between them and the state.
 
If they are making 450mm and working into more work into 22nm wafers either way. That is kinda impressive if not very impressive. Especially given the idea of multi-core processing and finding better ways to make those kinda of chips and give the a market value of something to work with on a consumers end. But on the idea of size though as well does add to the fact of to small of proc on a one wafer adds to wafer breaks mid process.
I myself am still a Core proc person/user, i like the idea of multi-proc but thats where im at with them though.
 
Bigger numbers always sound great in theory, but quite a few industry insiders think this is a bad idea, and will be very challenging. I expect 22nm to be a nightmare of a node for everyone, but Intel is just asking for trouble with this. I'd even say that 22nm will be exponentially worse than 40nm was for TSMC, or 32nm was for Intel.

Intel did a fine job of PRing their 32nm woes away, but there's a reason why they've not release a proper quad core 32nm chip, only low end dual cores, and high end 6 core chips that are ridiculous overpriced for the sole reason that their yields are too piss poor to manufacture in any real quantity.
 
[citation][nom]alidan[/nom]well right now we have 45nm with 8 cores, expect 22 to have around 16, or possibly more l1,2,3 cashes or current 6 core and 12 logicals to be about half price (possibly between 1/3 and 1/2)what i want to know is what 450mm is. is it bigger than what they are currently using[/citation]
Isn't it 50% larger wafers? 300 mm is common.it's huge and not an easy task to go bigger without risk of more waste or scrap wafers,QC.
 
[citation][nom]agnickolov[/nom]Current production uses 300mm wafers, so yes - it's definitely bigger, 2.25 times bigger in fact (1.5 times the diameter squared)[/citation]


The area of a circle is pi x (radius) squared

So basically we go from 221,841mm of area to 499,142mm (2.25 times bigger) your math was correct, just not the formula. This number is a bit deceptive however, since chips shot on the edge are often incomplete and more likely to suffer defects, so increasing the overall circumference will increase the number of defects, but it's worth it. It was ten years ago that 300mm was in development and in the early 2000's we transitioned from 200mm (eight inch wafers), this was very important to increasing the total production volume in order to keep up with the exponential increase in development costs. 22nm will push the border of current generation immersion lithography, and will most likely cross over to EUVL (Extreme UV Lithography) at the die shrink from 22nm to 16~15nm which should happen some time in late 2012 or early 2013. EUVL is still too expensive and has a high rate of defects, so we probably won't see any products from this process until 2013 in either case. Double-patterning and improvements in immersion lithography technology will probably be extended until 450mm wafers are proven reliable. This is the only way to improve semiconductor nodes while reducing prices.
 
[citation][nom]razor512[/nom]and prices will still be the same.How many times have the physical shrinking promised lower prices and the average price never actually lowers, but instead they tend to get more expensive?When they say cost savings they mean for them self and not for the customer, they will still take their massive markups.[/citation]

Bollocks. The price for computation continues to fall. Consider this: A current model quad-core Xeon workstation running at 2.66 GHz will outperform a multimillion dollar Cray C90 supercomputer used in the early 1990s

An nVidia Fermi GTX 480 is capable of 1345 Billion Floating Point Operations per Second (GFLOPs). That's 1.345 TFLOPs

The first computer to achieve that speed was brought online in 1997, it was called "ASCI Red" in Sandia Labs New Mexico. http://www.sandia.gov/ASCI/Red/index.html

ASCI Red cost $65,000,000; took almost two years to construct, and used almost 1 Mega-watt of electricity to operate.

An nVidia Fermi GTX 480 can be purchased on newegg.com for $369.99 after rebate.

Yeah, that's right. $65 million worth of computation in 1997 can be bought in 2010 for about the same price as a modest color television.


 
[citation][nom]JeanLuc[/nom]Why stop at 450mm? Why not 500mm, 600mm, 800mm etc? As interesting as it to read these stories I wish the news articles would explore the subject matter in greater detail.[/citation]

We're talking about thin sheets of glass-like material here. Increasing the size of such thin and fragile material is harder than it sounds, especially when a few nanometers of error can result in an entire wafer being worthless junk. 450mm wafers are probably the biggest challenge the semiconductor industry has ever faced. An entire new fab has to be built just to support it, and that costs billions of dollars just in construction, plus dozens, even hundreds of independent companies in the industry have to coordinate and agree to key specifications to ensure universal compatibility. New photo-resist chemicals need to be developed, temperature control, transportation, and so on; all new factors with unique obstacles. One 450mm wafer will contain about 3,000 chips, each of which will contain about 1 billion transistors or more. This isn't exactly a cake walk.
 
[citation][nom]f-14[/nom]i do not understand why intel chooses to build in earthquake country. the labor is cheaper there as well as taxes and other factors, but that would all get negated by the tremors they have all the time on the west coast.must have been on heck of a sweet $$$ deal brokered between them and the state.[/citation]

Most semiconductor manufacturing equipment and technology are developed in Asian countries (Japan and Taiwan) where tremors are constant. Anti-vibration technology is very mature, and simple steps can be taken to ensure that ground movement is minimal. Quakes in Oregon are typically very small, and larger quakes are fairly rare.
 
So, Okay, after all the comments on how and why and what does it mean and the rest , can someone please tell me which on tastes better?
It's like wafer this and wafer that, wafer here and wafer there, then comes the chinese wafers...... OMG.... and I can't get one to eat.....
 
Instead of being able to manufacture say 20 chips on one wafer at its current size, a larger wafer could produce say 35 chips at it's current size. Since theyre also looking to shrink the chip size they could be able to cram say 80 chips on the larger wafer... More chips created in less time and more economical to boot = lower prices for consumer.... or maybe a little less for the consumer and more profit for the manufacturer.
 
[citation][nom]ajax dev[/nom]Bigger numbers always sound great in theory, but quite a few industry insiders think this is a bad idea, and will be very challenging.[/citation]
And how many chips have these "industry insiders" produced?
 
One conceptual metric I like is cost per transistor. The combined effect of larger wafers and smaller features means that the cost per transistor drops through the floor as it has done in the past. That is why graphics are migrating to soc for most users. It's cheap to do and responsive to typical user needs even if special interest groups like gamers and high end graphics still require a supplemental card. Intel's revenue per transistor has dropped precipitously throughout its history. Gross revenues go up because people like lots of well designed transistors. Intel's dedication to Moore's Law means that they have to pop $6-8 billion for new facilities every couple of years to keep dealing with the decline in revenue per transistor. Translated, that means they need killer margins or else you can't do the new stuff that requires more and cheaper transistors.
 
Ok, so the simple answer is, it's hard as hell to uniformly spin and control the large silicon ingots used to make the wafers. It has to be so consistant and uniform that it's considered a single crystal of silicon, any any flaws means multiple wafers are defective from the start.
This site will give you an idea of the process. http://www.memc.com/index.php?view=Process-Animations-
If you think you can bump it to 800mm wide ingots as well as the do now, go for it because there's someone willing to pay you lots for that info.
 
[citation][nom]masterbinky[/nom]Ok, so the simple answer is, it's hard as hell to uniformly spin and control the large silicon ingots used to make the wafers. It has to be so consistant and uniform that it's considered a single crystal of silicon, any any flaws means multiple wafers are defective from the start.This site will give you an idea of the process. http://www.memc.com/index.php?view=Process-Animations- If you think you can bump it to 800mm wide ingots as well as the do now, go for it because there's someone willing to pay you lots for that info.[/citation]
Interesting site you linked, thanks for that!
 
[citation][nom]alidan[/nom]well right now we have 45nm with 8 cores, expect 22 to have around 16, or possibly more l1,2,3 cashes or current 6 core and 12 logicals to be about half price (possibly between 1/3 and 1/2)what i want to know is what 450mm is. is it bigger than what they are currently using[/citation]

I think they currently have 300mm, because I remember the news when they moved to a bigger wafer back then. So 450mm is bigger.
 
[citation][nom]f-14[/nom]i do not understand why intel chooses to build in earthquake country. the labor is cheaper there as well as taxes and other factors, but that would all get negated by the tremors they have all the time on the west coast.must have been on heck of a sweet $$$ deal brokered between them and the state.[/citation]

There never any earthquakes here in Oregon. Where not California.
 
Larger wafers mean that there will be a greater number of chips produced per cycle, which generally means a reduced cost on the producer that translates to lower prices for the consumer.
Click to expand...
Umm, this is Intel we are talking about, right? They have no competition, this is a company that has been selling $1000 chips for use in personal computers, who really believes Intel isn't going to keep their prices relatively steady and pocket the savings for additional R&D?
 
[citation][nom]f-14[/nom]i do not understand why intel chooses to build in earthquake country. the labor is cheaper there as well as taxes and other factors, but that would all get negated by the tremors they have all the time on the west coast.must have been on heck of a sweet $$$ deal brokered between them and the state.[/citation]
I live a couple miles from the San Andreas fault line in southern California, yet we rarely have earthquakes that are even noticeable. The last major earthquake was well over 10 years ago and most damage was done to older buildings not designed to withstand earthquakes. I highly doubt this location would be more tectonically active than where I live!
 
I worked at Intel few years back in Metrology. Just FYI - "300mm" is the diameter of the silicon wafer (grown as ingots and then diced into thin circular disks). They are the base to which all subsequent layers are built upon and then layer diced into individual processors. The current fabs are 12" (300mm). The move to 450mm requires new tools (machines that process the wafers) so its not a simple matter to go larger. Also - the larger the wafer, the thicker it will have to be to retain its strength.
 
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