Is Intel that bandwidth Starved?

[MatTheMurdera]

I ask because if they were then why do conroe or even the quadcore preliminary benchmarks show a fairly good improvment? I realize it should only be taken at face value, but assuming they are ligit, what does it mean? HT is low latency and very high bandwidth so if intel switched would it realy make that much of a difference? Also why do some benchmarks go up if bandwidth goes up even if it cant saturate it? For example the TH test of PCI-Express with 1,2,4,8 and 16 lanes, that showed improvments all the way up to 16X, but it was only 1-0.5 FPS after 4X. Gah! Im so confused!

 

[BaronMatrix]

I ask because if they were then why do conroe or even the quadcore preliminary benchmarks show a fairly good improvment? I realize it should only be taken at face value, but assuming they are ligit, what does it mean? HT is low latency and very high bandwidth so if intel switched would it realy make that much of a difference? Also why do some benchmarks go up if bandwidth goes up even if it cant saturate it? For example the TH test of PCI-Express with 1,2,4,8 and 16 lanes, that showed improvments all the way up to 16X, but it was only 1-0.5 FPS after 4X. Gah! Im so confused!

No, the rotation of the Earth prevented them from usng the SuperHyper Core mode as AM would say.
:lol:

 

[FITCamaro]

The power of marketting my friend.

 

[MatTheMurdera]

what?

 

[Heyyou27]

Intel would benefit from a HTT style bus system, but they're still doing fine with the northbridge. Once we get to 4-8 cores HTT really becomes more useful.

 

[Dante_Jose_Cuervo]

Well the current or just recent generation of P4s and PDs weren't really bandwidth starved, as you said it was the latency that was the problem because of the Netburst architecture. The reason Conroe is doing so well despite having higher latency and lower bandwidth than HT is because it's more efficient. That is, it makes better use of what bandwidth it has. And the reason the fps only went up like a tiny amount from 4X to 16X on the PCI-E tests were because of the same thing. It's not how much bandwidth you have available, it's how much of that you actually use.

 

[MatTheMurdera]

well it was tape that blocked some of the lanes and it was all on the same card. Im still not understanding why 8X to 16X would make any difference, the latency is the same, the way the card uses it is the same, the only difference is bandwidth and FPS, this would imply it needs more, but if it did why was there only a very small difference From 4X to 8X and 16X?

 

[kitchenshark]

C'mon guys, it's a legitimate question, very unlike a lot of posts as of late. A true techical question that I wouldn't mind knowing the answer to as well.

The answers given already are food for thought. I hadn't thought about it before but it is surprising that the northbridge solution is still keeping up.

 

[cxl]

Just my 0.02:

I believe that all that "low latency" and "higher bandwidth" of integrated memory controller has a lot to do with a quality of K7 3rd party chipsets, which were notoriously known for low(er) memory perfomance that Intel chipsets for Pentiums.

Therefore integrating memory controller on die brought all that nice performance improvements for K8. That is IMHO the real source of this "memory starved" legend. (Meanwhile, P4 Netburst sucks regardless of memory latency.)

 

[MatTheMurdera]

Good answer. Another thing I just remembered was that Intel is coming out with Duel FBS for the server market i think, anyway Intel knows more than me about Intel stuff so I assume Bandwidth may be an issue. And for Quad Core stuff another benchmark showed it wasnt scaling to well, thing was tho some people were saying it was feeling the bandwidth roof left over from Netburst, if it had, why was it showing any improvment at all?

 

[kitchenshark]

I would believe the GPU is a bottleneck itself for not using all the available bandwidth, along with CPU and memory performance. The way that I understand it is that the PCI-e standard was ... well, can't think of better words than 'over-engineered'.

Over-engineered on purpose to leave headroom for faster platforms and GPUs. That way the PCI-e standard would last for many years instead of quickly running out of expansion room.

 

[vimka]

Just my 0.02:

I believe that all that "low latency" and "higher bandwidth" of integrated memory controller has a lot to do with a quality of K7 3rd party chipsets, which were notoriously known for low(er) memory perfomance that Intel chipsets for Pentiums.

Therefore integrating memory controller on die brought all that nice performance improvements for K8. That is IMHO the real source of this "memory starved" legend. (Meanwhile, P4 Netburst sucks regardless of memory latency.)

Not to discount all of what is said here, but, didn't nVidia - a 3rd party chipset maker - pioneer the dual-channel DDR technology? Wasn't it the nForce2 chipset that first had this technology, now seen in all chipsets (excluding some budget systems)? I agree that most of AMD's 3rd party chipset makers were not up to the standards of Intel, but I think some (nVidia specifically) exceed them.

I believe the reason the on-die memory controller created such a leap in performance was that the CPU no longer had to address the Northbridge in order to access the memory. To use a metaphore - imagine if every time you wanted to speak to somebody, for any reason, you had to go through a 3rd party. You give them the message, they give it to your friend/family/pizza delivery guy, who then gives the response to the 3rd party, who then comes and gives the response to you. Just think about how much less efficient that is than just talking to them yourself. That, in a very lay-nutshell, is why ODMC is more efficient than a Northbridge.

 

[Topota_madre]

Intel is coming out with Dual FBS in order to keep enought bandwich to dual QuadCores, with 2 dual cores one simple FSB is enought.
AMD processors have to talk with the IMC too, it is beetwen the Cache and the memory, the same as the Northbridge.
Intel is going to put IMC and CSI in the next gen of Itanium but not for little systems because they don't need it. Problem with FSB starts when you add cores.

 

[theboomboomcars]

A good analogy for the bandwidth problem is to compare it to a freeway. If you have a very busy 2 lane freeway with a speed limit of 55, you are going to have lots of congestion. You can fix it in two ways you can add more lanes or increase the speed limit (ideally both). If you increase the speed limit you will see marginal improvement for travel times during busy times and a lot of improvement when there isn't as much traffic, if you increase the number of lanes you will see more improvement during busy times but no improvement during slower times. But if you do both you get lots of improvement.

So with the pci-ex there isn't enough traffic (yet) to really need all the extra lanes.
With fsb there is lots of congestion so raising the speed will see a slight improvement during heavy traffic and lots of improvement during light traffic. The HTT adds lots more lanes and keeps increasing the speed, which is why it is so nice, especially with heavy traffic, 4 or 8 way systems under load.

 

[MatTheMurdera]

ur not answering my questions, im asking not what makes something bandwidth starved and how to fix it, im asking are conroe and quad core starved. also im asking why there is ANY benafit (as seen in the PCI-express TH article) when extra bandwidth is added way above and beyond what the roof for use is.

 

[Action_Man]

What, another stupid post from BM? Say it isn't so.

 

[MatTheMurdera]

It isnt so. Damn didnt work.