Archived from groups: comp.sys.ibm.pc.hardware.chips (More info?)
Yousuf Khan wrote:
> K Williams <krw@adelphia.net> wrote:
>>> Well, it's a dual-channel in the sense that the processor reads
>>> the lower 64-bits from the first DIMM and the upper 64-bits from
>>> the second DIMM. I don't think it actually puts the two chips in
>>> separate banks and does bank interleaving in the traditional
>>> dual-channel sense. This is how Pentium 4's dual-channel works
>>> as well.
>>
>> How is this different than interleaving? An address and command
>> is sent to both channels and each fetch (in the burst) comes from
>> alternating channels. There are still two independent sets of
>> wires for the two channels, no? Otherwise I don't see what
>> dual-channel buys, electrically (note that I haven't looked that
>> closely).
>
> Well, I guess it's just that in this case, both DIMMs are really
> just extensions of one another inside the same bank. One
> row-column address is asserted that activates both DIMMs. Whereas
> in the bank-interleaved dual-channel, there has to two separate,
> but simultaneous, invocations of rows and columns, one for each
> bank since they each DIMM resides in separate banks.
I don't see the difference, except in some picky details. In reality
that's all they are in an "interleaved" memory system too. Both
leaves get the same address and they respond *interleaving* the
data. On the classical systems, the interleaved banks would share
the data bus, as well. Here they're completely separate, since the
bus bandwidth is completely used without "interleaving". ...still
not really anything new. It's not like the different controllers
are fetching from different places in memory.
--
Keith
Yousuf Khan wrote:
> K Williams <krw@adelphia.net> wrote:
>>> Well, it's a dual-channel in the sense that the processor reads
>>> the lower 64-bits from the first DIMM and the upper 64-bits from
>>> the second DIMM. I don't think it actually puts the two chips in
>>> separate banks and does bank interleaving in the traditional
>>> dual-channel sense. This is how Pentium 4's dual-channel works
>>> as well.
>>
>> How is this different than interleaving? An address and command
>> is sent to both channels and each fetch (in the burst) comes from
>> alternating channels. There are still two independent sets of
>> wires for the two channels, no? Otherwise I don't see what
>> dual-channel buys, electrically (note that I haven't looked that
>> closely).
>
> Well, I guess it's just that in this case, both DIMMs are really
> just extensions of one another inside the same bank. One
> row-column address is asserted that activates both DIMMs. Whereas
> in the bank-interleaved dual-channel, there has to two separate,
> but simultaneous, invocations of rows and columns, one for each
> bank since they each DIMM resides in separate banks.
I don't see the difference, except in some picky details. In reality
that's all they are in an "interleaved" memory system too. Both
leaves get the same address and they respond *interleaving* the
data. On the classical systems, the interleaved banks would share
the data bus, as well. Here they're completely separate, since the
bus bandwidth is completely used without "interleaving". ...still
not really anything new. It's not like the different controllers
are fetching from different places in memory.
--
Keith
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