Besides the memory spec, it's also worth noting that the last-gen Zen 4 CPUs peaked at 96 lanes of PCIe 5.0, as opposed to the claimed maximum of 120 PCIe 5.0 lanes with this motherboard.
That's NOT correct. Kind of misleading info. 96 PCIe lanes are only applicable for the EPYC 8004-series processors codenamed SIENA. These are based on the
SP6 socket.
Compared to the total 128 lanes of the connectivity found in the Genoa and Bergamo chips. 128 lanes of PCIe Gen 5 connectivity to peripherals (96 lanes in the EPYC 8004 Series and up to 160 lanes in EPYC 9004 Series 2-socket designs).
The exact same I/O die is being used in all 4th Gen EPYC processors, however their capabilities vary with how the die is
connected to the outside world.
To put it in simple terms, the larger SP5 package can enable pins to carry 128 lanes of I/O bandwidth and 12 memory channels. The smaller SP6 package has fewer pins, so obviously the I/O die is connected to 96 lanes of I/O connectivity and six memory channels.
Also, the Tweet has got all the info wrong on the SP5 socket. Those specs are not very clear, including the PCIe lanes. I don't have time to go into much details, but take those leaked spec data with some caution.
SP5 already supports 12 channels and 6 TB of RAM. Is this just a particular system supporting less?
I think these specs should apply only for the Zen 5C cores. Since the upcoming TURIN lineup will be based on
both Zen 5 & Zen 5C core architectures, these lower specs could be for a different SOCKET
config, mostly sporting Zen 5C "dense" cores.