Need SuperTech Help

[Guest]

I have an Abit BE-6.II mobo. The manual says that
1. PCI slot 5 and my Highpoint IDE controller use the same Bus master control signals, and
2. PCI-slot 3 shares IRQ signals with the HPT controller.
The manual also gives advice to use only IRQ sharing enabled devices in PCI.3.
What is the effect of slot 5 sharing bus master signals, and slot 3 sharing IRQ's.
I had a serious problem using my ATI-TV wonder card in this box: the computer would not recognize my WD205BA harddrive at all (slave drive; connected to HPT controller). This would also cause serious system hangs (not recognizing WD-drive at POST) and BSOD's. After removing the TV card, I had to boot with the WD-drive disconnected to get a complete boot. After a few successful boots, I plugged it back in and it worked fine. During this time I did not adjust any bios settings.
Are these symptoms related to the PCI sharing of bus mastering or IRQ's. It seems that it would be I mobo incompatibility since the drive wasn't recognized during boot up.
I really don't understand the Bus Mastering Sharing at all. Is there a practical effect, or some incompatibilities that I should be aware of?
Please post response, but cut/paste and email to td873@hotmail.com

thanks
thomas davis

 

[Guest]

I thomas,

the PCI bus is a fast bus able to make bursts (data are put on the bus at each clock cycle).
The bus is shared among several devices, and only the device that owns the bus can use it. To get the bus (more precisely to be the master of the bus and perform bus mastering which is the most efficient way to transfer data !), there is an arbiter somewhere, and each device has a request and grant wires to the arbiter. Bus access is mechanical.
Unforntunately, The arbiter has a limited set of request/grant pairs, and as the number of slot is increasing, some request/grant pairs must be shared. this is not a problem if one device does not make bus matering and thus does not use its REQ/GRT pair.
I don't know what is the highpoint controller, bus as it is related to IDE, I suspect it does bus mastering. So insert on the 5th slot a board that does no bus mastering !

For interrupts, it is the same problem of available number of wires, but the IRP can easily be shared on the PCI bus. It is the operating system and interrupt handlers to activate the right interrupt handler in response to an interrupt. The only problem is that if you connect on the same interrupt line 2 boards and one board generates a lot of interruptions, then the other board may be disturb. So in your slot 3, insert the board that does not generate a lot of interrupts.

Hope this will help.
By !
denis