Question PCIe Interconnect, RDMA, and Cache Coherence ?

[eonial]

I'm fairly a newbie in computer system research and recently encountered a thought on modern bus interconnect in computer systems while I was looking at RDMA documents.
As far as I understood (might be wrong), RDMA needs some memory region to be registered and through the registration process, a RDMA device becomes aware of physical address of registered memory.

Does it mean that the registration process will have OS pin (lock) the memory region so that it can't be swapped out to disk?
Also how RDMA read/write (one-sided verbs) guarantee cache coherence if CPUs have duplicate or updated blocks of the memory in their cache? Does OS do something to make the memory region non-cached region?
I'm having hard time understanding this and it really got me wondering how RDMA devices access system memory. Can anyone provide keywords or materials on how PCIe interconnect or legacy bus technology works in general?

I would appreciate any help.

 

[alceryes]

I'd think there's got to be a lock, otherwise the data needs to be brought back to memory before an operation can be performed.
It looks like you are wanting specifics on cache/memory coherence as it relates to RDMA. Hopefully, these articles can help - https://scholar.google.com/scholar?q=rdma+memory+coherence&hl=en&as_sdt=0&as_vis=1&oi=scholart

 

[eonial]

I'd think there's got to be a lock, otherwise the data needs to be brought back to memory before an operation can be performed.
It looks like you are wanting specifics on cache/memory coherence as it relates to RDMA. Hopefully, these articles can help - https://scholar.google.com/scholar?q=rdma+memory+coherence&hl=en&as_sdt=0&as_vis=1&oi=scholart

Appreciate it! For those who have the same question with me, I started with PCI Express Primer and it's been super helpful. I'll definitely take a look at those articles too!